Dave Scott is Principal Architect at Real Intent. He has been at Real Intent for a little over one year and has gotten a lot better at table tennis, besides being apprenticed as R&D on Implied Intent Verification. He was drawn into EDA verification software development more than 20 years ago … More »
January 29th, 2015 by David Scott
A couple of weeks ago I met Dan Hafeman and another friend for beer in Sunnyvale. I’ve worked with Dan twice: first when he was an executive and co-founder of IKOS Systems, and again at the Educational Garden at Full Circle Farm in Sunnyvale, which he now manages.
The discussion we had turned to the best idea he ever had in his career: what we used to call “co-modeling”. It led to IKOS’ largest ever sale in 2000. Because I’m now more plugged into the verification world than he is (though he remains much more in touch with kale and broccoli), I was able to congratulate him that this is now a mainstream verification technique when using emulators.
Co-modeling was what we used to call transaction interfaces to emulators — in other words, using the Accellera standard SCE-MI 2 interface. When it was new, no one quite knew what to call it. The IKOS press release in 2000 called it the “data streaming portal” because that seemed the best way to position it.
Dan says the idea first popped up in 1985 when IKOS had to re-vamp its initial product offering. IKOS had created a product for driving signals into a hardware accelerator. Over time this evolved into the mixed-level interfaces to HDL simulation implemented by the NSIM accelerator, but this was not really the most efficient modeling interface. Accelerators and emulators may be fast, but interfaces to them are not. You want to make a single data transfer count for a lot (i.e., a lot of verification cycles) with a high-level transaction. Read the rest of A Personal History of Transaction Interfaces to Hardware Emulation: Part 1
January 22nd, 2015 by Graham Bell
Intel recently announced its new fifth generation ‘Broadwell’ processor chips for personal computers, laptops and server. Using 14nm geometry the new line of CPUs offers a lower power footprint, better throughput for multimedia, while keeping computing performance flat.
The following graphic outlines that the raw number of transisitors has grown 35% to 1.4 billion for an i7 CPU. The TDP (total dissipated power) for theses designs is only 15W. It can throttle back to 7.5W for even lower battery burn.
For server applications, the CPUs are even larger to almost 2 billion transistors. Total power tops out at 28 watts.
January 18th, 2015 by Graham Bell
Like other successful design automation companies we have many happy customers that use our tools. Marketeers like myself crave getting customer stories and comments to share with the world at large. While an individual engineer is happy to share his point of view why he likes one of our tools, before it can be made public and ascribed to engineer X at company Y, it must pass through a gauntlet of approvals by upper management at the customer. Often there is a “quid pro quo” in this process. In other words, to get company management to approve the quote, some benefit in the form of additional pricing discount, or extra short-term licenses is negotiated. Or sometimes management sees Real Intent’s static solutions as one of their ‘secret weapons’ and don’t want to share the good news with potential competitors.
January 8th, 2015 by Graham Bell
Real Intent and its distributor Claytronic Solutions participated this week at the the 28th International Conference on VLSI Design in Bangalore, January 5-7.
The conference is hosting industry’s first IoT-Ideathon, a 60 – hour long event, in which over 100 students and young professionals are taking part and to create 25 new and innovative applications in the internet-of-things.
In keeping with the IoT theme, Infosys co-founder Nandan Nilekani Monday predicted emergence of smart phones with biometric sensors in a keynote address.
“As biometric sensors get popular and cheaper, the next generation of smart phones will have iris cameras built into them. In a year or two, we will have sub-$100 smart phones with an iris camera that does authentication of the Aadhaar number,” Nilekani, a former Unique Identification Authority of India (UIDAI) chief.
December 18th, 2014 by Graham Bell
May you enjoy health, happiness, and peace in this holiday season and through the coming year!
From the staff at Read the rest of Seasons Greetings from Real Intent!
December 11th, 2014 by Graham Bell
Real Intent has had an exciting 2014! In the last few months we have announced a new release of Meridian CDC , new distribution partners in Taiwan and India, and seen many of you at trade shows in Silicon Valley, China, Israel, Japan, Germany and the United Kingdom. Our YouTube video channel keeps you up to date on all the latest developments at Real Intent, with our most recent on the New 2014 Release of Meridian CDC Meets Challenge of Billion-gate SoCs. I also discussed “Beer, New Meridian CDC, and Arnold Schwarzenegger?! ” with Sean O’kane of ChipEstimate in an ARM TechCon video interview.
There have been over 50 postings on the Real Talk blog this year, and I have selected the most popular ones read by the EDACafe audience. Here are the top five:
As you can see clock-domain crossing (CDC) remains a very hot topic. Look for more postings on this sign-off requirement in the coming year.
December 4th, 2014 by Graham Bell
The IEEE announced in September that is was launching working a on a new power standard called P2415. This blog gives the background for this new effort.
The current low power design and verification standard (IEEE 1801-2013 and IEEE P1801) is focused on the voltage distribution structure in design at Register Transfer Level (RTL) description and below. It has minimal abstraction for time (having only an interval function for modeling clock frequency), but depends on other hardware oriented standards to abstract events, scenarios, clock trees, etc. which are required for energy proportional design, verification, modeling and management of electronic systems. The necessary abstractions of hardware, as well as layers and interfaces in software are not yet defined by any existing standards. Read the rest of P2415 – New IEEE Power Standard for Unified Hardware Abstraction
November 27th, 2014 by Dr. Pranav Ashar
This article was originally published on TechDesignForums and is reproduced here by permission.
It’s tempting to see lint in the simplest terms: ‘I run these tools to check that my RTL code is good. The tool checks my code against accumulated knowledge, best practices and other fundamental metrics. Then I move on to more detailed analysis.’
It’s an inherent advantage of automation that it allows us to see and define processes in such a straightforward way. It offers control over the complexity of the design flow. We divide and conquer. We know what we are doing.
Yet linting has evolved and continues to do so. It covers more than just code checking. We begun with verifying the ‘how’ of the RTL but we have moved on into the ‘what’ and ‘why’. We use linting today to identify and confirm the intent of the design.
A lint tool, like our own Ascent Lint, is today one of the components of early stage functional verification rather than a precursor to it, as was once the case.
November 20th, 2014 by Graham Bell
To satisfy demands for lower-power and higher performance, the use of multiple CPU cores is a norm in SoC design. The interaction of multiple cores and the surrounding semiconductor IP, presents new challenges to verification. But what about EDA tool providers? How can the use of multple CPUs improve performance and throughput in their tools? What software caveats do they need to be aware to support processing by parallel CPUs? Pranav Ashar, CTO at Real Intent gives his perspective below.
EDA tools must be exploit parallelism to keep up with SoC complexity, or we will be attempting to designing next-generation chips on what effectively will be antique hardware.
A couple of factors have combined to reduce the pace at which parallelism has been adopted in EDA tools. It is common to overlook the latency impact when designing parallel programs that communicate with physical memory. Cache-coherency and memory access latency are often encountered examples that lowers the processing throughput of a tool on a multi-core processor. Fine-grain multi-threading in EDA tools quickly triggers some of these latency bottlenecks – for the typical SoC benchmark, these limits are reached rather rapidly.
November 13th, 2014 by Graham Bell
Its a fact of life that semiconductor design is a world-wide activity, and that EDA companies are helping customers in a 24 hour day. How international is this world? According to the latest statistics from the EDA Consortium, over 50% of the business activity is outside North America. The total of EDA, semiconductor IP and design services revenue was 6.9 billion dollars in 2013. Comparing this to a world population of 7.1 billion means roughly one dollar per person was spent on the wide world of design.