Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
December 13th, 2012 by Graham Bell
I had the pleasure of attending the luncheon organized by the Design Verification Club of Austin on the mystical date 12/12/12. It was the concluding event at the Microprocessor Test and Verification Workshop which is held every year at this time. DVClub lunch-time talks are designed to share knowledge among the verification community and happen several times per year. Real Intent is a new sponsor for DVClub and we join sponsors such as Cadence, Oracle and Breker.
Eric Hennenhoefer, Director of Verification Enablement at ARM, who is a founder and organizer for DVClub generously participated in a video interview which can be seen below. I think these events are a good idea and look forward to sponsoring the next one in Silicon Valley at Dave & Busters in Milpitas on Feb. 7. The talk will be given by Dean Drako, CEO & President, IC Manage.
At the Austin event, Zihno Jusufovic from AMD spoke on “Processor Verification of AMD’s ‘Jaguar': A next generation low power x86 core.” While Zihno declined to speak on camera about his talk (something about review by pesky lawyers), I was able to glean a few points. Zhino led what he described as a small verification team and they needed to use several strategies to use their resources efficiently. Here is what I learned:
December 4th, 2012 by Jim Foley, Director of R&D, Real Intent
This is the second in our series on lint rules, where we discuss various coding issues and how to improve the quality of RTL designs. The lint rule for this month is OPEN_INPUT.
How many different ways can you express nothing? And do you mean the same thing each time?
It’s not as if Ascent Lint has a rule that will look for nothing and point out to you where nothing is discovered. There is a whole category of rules for this! Over 30 rules in the Omission category will point out nothing in various situations with the general expectation that there should be a coding element, but it is missing.
Not all nothings are necessarily the same, however. Consider these three module instantiations:
funcBlock inst1 (.aa(xx), .cc(zz));
In late September, I blogged about the results of our DAC survey on CDC bugs, X propagation, constraints. Now for those of you who don’t know what CDC means, it is an acronym for Clock Domain Crossing. Lots of different clock domains are used because of the integration of different blocks and IP in modern SoCs. Not only must CDC be analysed, it is now becoming a sign-off requirement.
In our survey it showed that 62% of the respondents said that CDC bugs resulted in late ECOs. These bugs are affecting design schedules and design teams need to do thorough CDC verification. What are the other 28% doing? Some design teams tell us that their design methodology is immune to CDC issues. This is not typical for fabless semi design teams.
Chip Design Magazine has also been running a poll: Have you had CDC bugs slip through resulting in late ECOs or chip respins? on their web-site. If you go to ChipDesignMag.com and scroll half-down the page and on the left side you will see this:
I have been monitoring this poll for a while and there has not been a lot of recent activity. Feel free to go to the ChipDesignMag.com web-site and scroll down to cast your vote. Here are the results so far: Read the rest of Have you had CDC bugs slip through resulting in late ECOs or chip respins?
John Cooley’s DeepChip newsletter on Sept. 21 featured Real Intent’s 2012 DAC survey on CDC bugs, X propagation, constraints. It is
reproduced here below. Read the rest of DAC survey on CDC bugs, X propagation, constraints
Sarath Kirihennedige, Sr. Manager Product Engineering at Real Intent, speaks with Graham Bell on how design constraints (SDC) are currently developed, what are the problems with the current approach and what a complete Constraints management and verification solutions looks like.
Sarath was most recently at Cadence Design Systems in a senior product engineering role. He has held management level positions at Tera Systems, Mentor Graphics, and Exemplar. He is fluent in Japanese, and has been awarded a patent in the area of timing constraint verification.
A month ago in London, on the world’s biggest stage, Usain Bolt crossed the finish line of the fastest race on earth with his signature nonchalance. The moment belied a lifetime of passion, grit, determination, training and preparation, and in the sub-10 seconds prior, Bolt injected a super-sized dose of inspiration to millions and triggered motivational tsunamis worldwide. Moments like these are rocket fuel for people seeking to make a positive change in their lives, both personal and professional. In the latter, it serves to boost the morale of colleagues and teams in the organization they work for. Indeed, motivational theories abound with references to the need for both intrinsic and extrinsic forms of motivation for organizations to survive, compete and win, especially in today’s dynamic marketplace. This year, we at Real intent, are deriving our dose of extrinsic motivation from the Olympics and its inspirational athletes.
Frontrunners in our strong contingent of tools include Meridian CDC which accelerates advanced CDC sign-off and Ascent Lint which accelerates early functional verification. Read the rest of A Bolt of Inspiration
Chris Morrison, Chief Architect at Real Intent discusses the differences that set the Implied Intent Verification (IIV) tool apart from lint and simulation. He highlights the positive impact on RTL designs that have even 99% testbench coverage. This interview took play in July 2012.
Chris Morrison was employee #2 at Real Intent. He brings over 25 years of EDA software engineering experience to the team. Previous to Real Intent he led the engineering development of clock tree generation and placement based optimization tools at Cadence Design Systems. Prior to that he worked at Viewlogic Systems. His PhD is from the University of Colorado and BSEE is from Yale University. Chris has been awarded six patents in the areas of IC design and verification.