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Graham Bell
Graham Bell
Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »

Real Intent Reports on DVClub Event at Microprocessor Test and Verification Workshop 2012

December 13th, 2012 by Graham Bell

I had the pleasure of attending the luncheon organized by the Design Verification Club of Austin on the mystical date 12/12/12.  It was the concluding event at the Microprocessor Test and Verification Workshop which is held every year at this time.  DVClub lunch-time talks are designed to share knowledge among the verification community and happen several times per year. Real Intent is a new sponsor for DVClub and we join sponsors such as Cadence, Oracle and Breker.

Eric Hennenhoefer, Director of Verification Enablement at ARM, who is a founder and organizer for DVClub generously participated in a video interview which can be seen below.  I think these events are a good idea and look forward to sponsoring the next one in Silicon Valley at Dave & Busters in Milpitas on Feb. 7.  The talk will be given by Dean Drako, CEO & President, IC Manage.

At the Austin event, Zihno Jusufovic from AMD spoke on “Processor Verification of AMD’s  ‘Jaguar': A next generation low power x86 core.”  While Zihno declined to speak on camera about his talk (something about review by pesky lawyers), I was able to glean a few points.  Zhino led what he described as a small verification team and they needed to use several strategies to use their resources efficiently.   Here is what I learned:
Read the rest of Real Intent Reports on DVClub Event at Microprocessor Test and Verification Workshop 2012

Ascent Lint Rule of the Month: OPEN_INPUT

December 4th, 2012 by Jim Foley, Director of R&D, Real Intent

This is the second in our series on lint rules, where we discuss various coding issues and how to improve the quality of RTL designs. The lint rule for this month is OPEN_INPUT.

How many different ways can you express nothing? And do you mean the same thing each time?

It’s not as if Ascent Lint has a rule that will look for nothing and point out to you where nothing is discovered. There is a whole category of rules for this! Over 30 rules in the Omission category will point out nothing in various situations with the general expectation that there should be a coding element, but it is missing.

Not all nothings are necessarily the same, however. Consider these three module instantiations:

funcBlock inst1 (.aa(xx[1]), .cc(zz[1]));
funcBlock inst2 (.aa(xx[2]), .yy(), .cc(zz[2]));
funcBlock inst3 (xx[3], , zz[3]);

Read the rest of Ascent Lint Rule of the Month: OPEN_INPUT

Real Intent Has Excellent EDSFair 2012 Exhibition

November 19th, 2012 by Graham Bell

Real Intent showcased and discussed its two product families – Ascent™ for early functional verification before synthesis; and Meridian™ for advanced sign-off verification for CDC and timing constraints, at the EDSFair in Yokohama City in Japan, Nov. 14-16. Our country Manager at Real Intent KK, Yasuo Torisawa, and Senior Application Engineering Manager, Kazutaka Kanda, met with a large number of visitors at its booth.  The reception to Real Intent’s best-in-class products was excellent and many new business discussions were started.
Here below are some pictures taken at the Real Intent booth.

Ascent Lint Rule of the Month: ZERO_REP

November 5th, 2012 by Jim Foley, Director of R&D, Real Intent

Ascent Lint can check your RTL design against hundreds of rules and coding checks.  The problem is, how can I tell people about them?  You’ve got more important things to  do than to slog though all the details of what Ascent Lint can do for you and your HDL design. Then it occurred to me that maybe the best way to talk about these rules is one at a time.  That way, you get some useful information, and you and I can both get to our pressing list of t0-dos. I want to discuss our first Lint Rule of the Month, ZERO_REP.

In Verilog, a replication concatenate expression { C { expr } } means that the value of expr is copied C times and concatenated together to produce the result.  For understandable reasons, the first version of the Verilog simulator made the reasonable assumption that any logic expression will have some length greater than zero, so it evaluates { 0 { expr} } to be 1’b0. Since then, the Verilog language been standardized in IEEE-1364, commonly referred to as the Language Reference Manual, or LRM for short. The committee that determined how things should work observed that zero copies of an expression ought to result in an expression with zero length, provided that it was then concatenated with something else of some non-zero length, again to avoid the problem of a zero length value by the time it is assigned to something else.

Read the rest of Ascent Lint Rule of the Month: ZERO_REP

You did Clock Domain Crossing (CDC) analysis, but do you have CDC sign-off?

October 22nd, 2012 by Graham Bell
You did Clock Domain Crossing (CDC) analysis, but do you have CDC sign-off?
Join us for a European Webinar on October 25
Space is limited.
Reserve your Webinar seat now at:
Real Intent’s Meridian Clock Domain Crossing (CDC) software ensures that the signal crossing and integrity of asynchronous clock domains inside a chip are correct.  This webinar will cover the requirements to achieve CDC sign-off.Agenda:

  • Why Simulation and Timing Analysis is not sufficient
  • What’s necessary for sign-off:  Design, Verification, Methodology
  • Requirements for environment setup, full-chip analysis
  • Advanced technology: intent inference and metastability aware formal
  • Question and Answers
Title:   You did Clock Domain Crossing (CDC) analysis, but do you have CDC sign-off?
Date:   Thursday, October 25, 2012
Time:   2:00 PM – 3:00 PM CEST
After registering you will receive a confirmation email containing information about joining the Webinar.

System Requirements

PC-based attendees
Required: Windows® 7, Vista, XP or 2003 Server
Mac®-based attendees
Required: Mac OS® X 10.5 or newer
Mobile attendees
Required: iPhone®, iPad®, Android™ phone or Android tablet

Have you had CDC bugs slip through resulting in late ECOs or chip respins?

October 11th, 2012 by Graham Bell

In late September, I blogged about the results of our DAC survey on CDC bugs, X propagation, constraints.   Now for those of you who don’t know what CDC means, it is an acronym for Clock Domain Crossing.  Lots of different clock domains are used because of the integration of different blocks and IP in modern SoCs.  Not only must CDC be analysed, it is now becoming a sign-off requirement.

In our survey it showed that 62% of the respondents said that CDC bugs resulted in late ECOs. These bugs are affecting design schedules and design teams need to do thorough CDC verification. What are the other 28% doing?  Some design teams tell us that their design methodology is immune to CDC issues.  This is not typical for fabless semi design teams.

Chip Design Magazine has also been running a poll: Have you had CDC bugs slip through resulting in late ECOs or chip respins? on their web-site.  If you go to and scroll half-down the page and on the left side you will see this:

I have been monitoring this poll for a while and there has not been a lot of recent activity.   Feel free to go to the web-site and scroll down to cast your vote.   Here are the results so far: Read the rest of Have you had CDC bugs slip through resulting in late ECOs or chip respins?

DAC survey on CDC bugs, X propagation, constraints

September 27th, 2012 by Graham Bell

John Cooley’s DeepChip newsletter on Sept. 21 featured Real Intent’s 2012 DAC survey on CDC bugs, X propagation, constraints.   It is
reproduced here below. Read the rest of DAC survey on CDC bugs, X propagation, constraints

Video Interview: “SDC Management and Verification: What’s Missing?”

September 20th, 2012 by Graham Bell

Sarath Kirihennedige, Sr. Manager Product Engineering at Real Intent, speaks with Graham Bell on how design constraints (SDC) are currently developed, what are the problems with the current approach and what a complete Constraints management and verification solutions looks like.

Sarath was most recently at Cadence Design Systems in a senior product engineering role. He has held management level positions at Tera Systems, Mentor Graphics, and Exemplar.  He is fluent in Japanese, and has been awarded a patent in the area of timing constraint verification.

A Bolt of Inspiration

September 13th, 2012 by Vaishnav Gorur, Sr. Applications Engineer

A month ago in London, on the world’s biggest stage, Usain Bolt crossed the finish line of the fastest race on earth with his signature nonchalance. The moment belied a lifetime of passion, grit, determination, training and preparation, and in the sub-10 seconds prior, Bolt injected a super-sized dose of inspiration to millions and triggered motivational tsunamis worldwide. Moments like these are rocket fuel for people seeking to make a positive change in their lives, both personal and professional. In the latter, it serves to boost the morale of colleagues and teams in the organization they work for. Indeed, motivational theories abound with references to the need for both intrinsic and extrinsic forms of motivation for organizations to survive, compete and win, especially in today’s dynamic marketplace. This year, we at Real intent, are deriving our dose of extrinsic motivation from the Olympics and its inspirational athletes.

Frontrunners in our strong contingent of tools include Meridian CDC which accelerates advanced CDC sign-off and Ascent Lint which accelerates early functional verification. Read the rest of A Bolt of Inspiration

Video: Ascent IIV Finds RTL Functional Bugs that Simulation Can Miss

September 6th, 2012 by Graham Bell

Chris Morrison, Chief Architect at Real Intent discusses the differences that set the Implied Intent Verification (IIV) tool apart from lint and simulation. He highlights the positive impact on RTL designs that have even 99% testbench coverage. This interview took play in July 2012.

Chris Morrison was employee #2 at Real Intent.  He brings over 25 years of EDA software engineering experience to the team.  Previous to Real Intent he led the engineering development of clock tree generation and placement based optimization tools at Cadence Design Systems.  Prior to that he worked at Viewlogic Systems.  His PhD is from the University of Colorado and BSEE is from Yale University.  Chris has been awarded six patents in the areas of IC design and verification.

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