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Vinod Viswanath
Vinod Viswanath
Vinod Viswanath is a Director of R&D at Real Intent, where he works on next generation tools to understand and implement low power and timing constraints. Prior to this, he was a researcher in Intel’s low power group working on formal verification of processors and SOC platforms. Vinod … More »

UPF 3.0 – Making Power Intent Manageable, Incremental and Executable

 
April 7th, 2016 by Vinod Viswanath

UPF provides a consistent format to specify power design information that may not be easily specifiable in a design description. In certain situations it is undesirable to specify power semantics directly in the HDL, as doing so might tie down the implementation to certain power constraints. UPF provides a way to specify the power intent for different states and contexts, external to the design, to be used for implementation, modeling, simulation and verification. The semantics of UPF are consistent across implementation and verification, guaranteeing that what is being verified is indeed what was implemented.

UPF assumes a logical hierarchy that is a more abstract model of the design hierarchy. The logical hierarchy can be viewed as a conceptual structure for locating power management objects such as power domains and power states. Each object is defined in a specific scope of logical hierarchy. This logical hierarchy can be effectively used in a top-down UPF methodology, where the more abstract states are higher up in the hierarchy (global states), and the lower hierarchical objects are more refined versions of their ancestors. Read the rest of UPF 3.0 – Making Power Intent Manageable, Incremental and Executable

How Physical Implementation Can Break Your Clock-Domain Crossing Logic

 
March 31st, 2016 by Graham Bell

At DVCon’16, Mark Litterick presented a paper and presentation on “Full Flow Clock Domain Crossing – From Source to Si.”   Here is the abstract for the paper:

Functional verification of clock domain crossing (CDC) signals is normally concluded on a register-transfer level (RTL) representation of the design. However, physical design implementation during the back-end pre-silicon stages of the flow, which turns the RTL into an optimized gate-level representation, can interfere with synchronizer operation or compromise the effectiveness of the synchronizers by eroding the mean time between failures (MTBF). This paper aims to enhance cross-discipline awareness by providing a comprehensive explanation of the problems that can arise in the physical implementation stages including a detailed analysis of timing intent for common synchronizer circuits.

Mark works for Verilab as senior verification consultant and holds the position of fellow. He is based in Munich, Germany.  To see more of Mark’s technical papers, check out his profile page on the Verilab web-site.

Even though, you may have signed-off for CDC at RTL, logic synthesis, design-for-test and low-power optimization tools can break CDC at the gate-level, the physical implementation stage of design. Real Intent’s Meridian products provide clock-domain crossing verification and sign-off.  Our most recent offering is Meridian Physical CDC and provides sign-off at the netlist level of the design.  It uses a mix of structural and formal methods to identify  glitching and other errors that break the correct registration of signals crossing clock domains. Read the rest of How Physical Implementation Can Break Your Clock-Domain Crossing Logic

Informal, Unformal, or Appformal? …and new FormalWorld.org

 
March 10th, 2016 by Graham Bell

Around the Design and Verification Conference in San Jose at the beginning of the March, a lot of activity was happening in the online world in preparation for the big meetup of the verification community.

First, the DeepChip.com web-site published a set of five (5) articles that surveyed the world of formal verification in EDA, written by Jim Hogan, of Vista Ventures, a Silicon Valley investment firm.  Jim is currently on the Board of OneSpin, a formal tools company.  Knowing Jim, he did his homework before getting involved with them.  If you read the articles, which total 12,000 words, you will have to agree with me there is a lot of great content here.  If a technical writer charged for producing this, you would be looking at a bill close to $20,000.

These days you have to two general ways to verify the functionality of your RTL with formal.  You either write your own properties and then feed them and the RTL to a formal property verifier (FPV) tool, OR you have an application-focused formal tool  automatically read and apply properties to your design.

Read the rest of Informal, Unformal, or Appformal? …and new FormalWorld.org

DVCon Recap

 
March 3rd, 2016 by Graham Bell

The Design and Verification Conference in Silicon Valley delivered the goods again this year. Here are some quick highlights from the show.

Wednesday%20Afternoon-8[1]

Graham talking to Koko and Pippa at the Oski Tech booth.

Read the rest of DVCon Recap

Free Panels and Keynote at DVCon in Silicon Valley

 
February 25th, 2016 by Graham Bell

You will glad to know that the free Exhibits-Only registration for the Design and Verification Conference (DVCon) that is taking place Feb. 29 through Mar. 3,  gives you access to the Tuesday keynote by Wally Rhines of Mentor, and the two panels on Wednesday.  And don’t miss the Tuesday evening reception hosted by EDAC, which finishes with Jim Hogan speaking with Dr. Ajoy Bose (Atrenta) about his experiences building multiple successful companies.  Your DVCon registration gives you free access to this event.

Here are more details on the panels, one of which is organized by Real Intent.

Emulation + Static Verification Will Replace SimulationWednesday March 02, 1:30pm – 2:30pm | Oak/Fir Read the rest of Free Panels and Keynote at DVCon in Silicon Valley

The Times They are a-Changin': Gravity Waves, Moore’s Law, and Record Basketball

 
February 11th, 2016 by Graham Bell

Big changes happened this week.

First, gravity waves have been detected for the first time in an announcement on Feb. 11.  This confirms a major prediction of Albert Einstein’s 1915 general theory of relativity and opens an unprecedented new window onto the cosmos. Physicists have concluded that the detected gravitational waves were produced during the final fraction of a second of the merger of two black holes to produce a single, more massive spinning black hole. This collision of two black holes had been predicted but never observed.

The gravitational waves were detected by both of the twin Laser Interferometer Gravitational-wave Observatory (LIGO) detectors, located in Livingston, Louisiana, and Hanford, Washington, USA. The LIGO Observatories  were conceived, built, and are operated by Caltech and MIT.

Last March, researchers completed major upgrades to the interferometers, known as Advanced LIGO, increasing the instruments’ sensitivity and enabling them to detect a change in the length of each arm, smaller than one-ten-thousandth the diameter of a proton(!). By September, they were ready to start new observations and then saw the black hole merger. Read the rest of The Times They are a-Changin': Gravity Waves, Moore’s Law, and Record Basketball

Super Bowl 50, and Semiconductor and Design Predictions for 2016

 
February 4th, 2016 by Graham Bell

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The game will be played in the Silicon Valley city of Santa Clara.


Super Bowl 50 is being played this Sunday, Feb. 7 to determine the champion of the National Football League (NFL) for the 2015 season. It will be held at Levi’s Stadium in Santa Clara, California, between the National Football Conference (NFC) champion Carolina Panthers and the American Football Conference (AFC) champion Denver Broncos.  The game will be played about 6 miles from my house in the East Bay, but I will be enjoying the event on television.  There will be the usual collection of interesting commercials and the half-time entertainment will include the band Coldplay and feature Beyoncé and Bruno Mars.  My prediction is that the Panthers will beat the spread and defeat the Broncos by more than 6 points.  I have not made any cash bets. Yet.

Brian Bailey at SemiEngineering.com does an annual survey of companies in the semiconductor ecosystem for their predictions of what will happen in 2016.  His articles (Design; Semiconductor, Manufacturing and Design; Tools and Flows) published several of my comments.  I did want to share with you the rest of my predictions and they are all given below.  Enjoy! Read the rest of Super Bowl 50, and Semiconductor and Design Predictions for 2016

CDC Verification of Fast-to-Slow Clocks – Part 3: Metastability Aware Simulation

 
January 28th, 2016 by Dr. Roger B. Hughes, Director of Strategic Accounts

We continue the short blog series that addresses the issue of doing clock domain crossing analysis where the clocks differ in frequency. In Part 1 and Part 2, we discussed the use of structural and formal checks when there is a fast-to-slow transition in a clock domain crossing. In this blog, we will present the third and final step using a design’s testbench.

The next step in the verification process of fast-to-slow clock domain crossings is to do metastability-aware simulation on the whole design. When running a regular simulation test bench, there is no concept of what could happen to the design if there was metastability present in the data or control paths within the design. One of the key reasons for doing CDC checks is to ensure that metastability does not affect a design. After structural analysis ensures that all crossings do contain synchronizers, and formal analysis ensures that the pulse width and data are stable, a whole-chip metastability-aware simulation is needed to see if the design is still sensitive to metastability. Functional monitors and metastability checkers are shown in Figure 7. No changes are made to the design, and the necessary monitors and checkers are written in an auxiliary Verilog simulation test bench file. This auxiliary file is simply referred to by the original simulation test bench file to invoke the metastability checking. As a prerequisite, this step requires that the design have a detailed simulation test bench. Read the rest of CDC Verification of Fast-to-Slow Clocks – Part 3: Metastability Aware Simulation

CDC Verification of Fast-to-Slow Clocks – Part 2: Formal Checks

 
January 21st, 2016 by Dr. Roger B. Hughes, Director of Strategic Accounts

We continue the short blog series that addresses the issue of doing clock domain crossing analysis where the clocks differ in frequency. In Part 1, we ended the discussion noting that when there is a fast-to-slow transition, there is a possibility that a short duration control pulse may be completely missed by the receive domain and a formal analysis is required to discover if this is a potential problem. We will look at how formal analysis can verify this kind of transition.

A formal check also is required on a slow-to-fast data crossing with feedback. In such a circuit, as shown in Figure 4, an acknowledge signal coming from the receiving fast-clock domain to the transmitting slow-clock domain also requires a formal Pulse Width check. Although the control pulse (request) is going from slow to fast and does not need a formal pulse width check, the acknowledge pulse-width check is necessary because the acknowledge signal (the feedback circuit) is going from a fast to a slow clock and, in order for the acknowledge to be properly captured, the acknowledge pulse (transmitted from the receiving side) must be sufficiently wide to be captured (received on the transmitting side) by the slower clock domain of the transmitting side flops. Failure to check for this condition is the reason behind many a request/acknowledge circuit not working as expected. Note that feedback circuits in a fast-to-slow crossing are operating in a slow-to-fast mode and the acknowledge signal in such a circuit does not need to be pulse-width checked. In short, all fast-to-slow control signal transitions, whether connected in a feed-forward or a feedback manner need to be formally pulse-width checked to ensure integrity of the control aspect of the clock domain crossing. Read the rest of CDC Verification of Fast-to-Slow Clocks – Part 2: Formal Checks

CDC Verification of Fast-to-Slow Clocks – Part 1: Structural Checks

 
January 14th, 2016 by Dr. Roger B. Hughes, Director of Strategic Accounts

This is a reprise of  a short blog series that addresses the issue of doing clock domain crossing analysis where the clocks differ in frequency, and the use of three different techniques for a complete analysis.

INTRODUCTION

CDC checking of any asynchronous clock domain crossing requires that the data path and the control path be identified and that the receive clock domain data flow is controlled by a multiplexer with a select line that is fed by a correctly synchronized control line.  Meridian CDC will always identify all the data and associated control paths in a design and will ensure that the control signals passing from a transmit clock domain to an asynchronous receive clock domain are correctly synchronized.  There are three separate techniques that are used within Meridian CDC: structural checking, formal checks and simulation-based injected metastability checks.

Read the rest of CDC Verification of Fast-to-Slow Clocks – Part 1: Structural Checks

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