Open side-bar Menu
 Real Talk
Vaishnav Gorur, Sr. Applications Engineer
Vaishnav Gorur, Sr. Applications Engineer
Prior to joining Real Intent, Vaishnav was a logic design engineer at MIPS Technologies where he was responsible for the microarchitecture and RTL Design of the Load-Store Unit and Graduation Unit of the 15-stage out-of-order asymmetric dual-issue superscalar pipeline in the MIPS32® 74K® fully … More »

Lending a ‘Formal’ Hand to CDC Verification: A Case Study of Non-Intuitive Failure Signatures — Part 1

June 13th, 2013 by Vaishnav Gorur, Sr. Applications Engineer

In Austin, at the 50th DAC earlier this month,  I delivered a poster presentation on “Lending a ‘Formal’ Hand to CDC Verification: A Case Study of Non-Intuitive Failure Signatures”.   In this first blog in a series, I will set the stage for the issues around the case study of failures in a common clock domain crossing synchronizer.

At DAC 2012 last year, we surveyed more than 300 participants to understand trends in the CDC verification space.  More than half had a new design project starting within 3 months, which indicates reduced design cycles.  Almost 1/3rd had over 50 clock domains in their design. Extrapolating from our DAC 2011 survey, we see a definite trend of increasing CDC complexity.  Almost 2/3rd had to incur the penalty of an ECO due to a CDC bug.

For the reasons above, CDC Analysis tools topped their shopping list.

As CDC verification is becoming mainstream, it is imperative to refine and fine tune the CDC flow to balance the verification effort. As indicated by the pie-chart on the bottom-right, ‘Automatic Formal’ is another technology that the industry is looking to leverage. In this presentation, we show how the application of formal analysis in the CDC space can be used by design engineers to verify their CDC constructs and how this can alleviate the CDC verification challenge from the shoulders of verification engineers.

Read the rest of Lending a ‘Formal’ Hand to CDC Verification: A Case Study of Non-Intuitive Failure Signatures — Part 1

Photo Booth Blackmail!

June 6th, 2013 by Graham Bell

Real Intent had a photo booth at its exhibit in Austin this week at the Design Automation Conference.  I thought it would be cool to give a photo souvenir of the 50th conference for anyone who strolled by.  On hand to work the booth were Julia and Antonio and they helped everyone enjoy themselves.

We had lots of fun hats, glasses, props, and feather boas for dress up.   Between Julia and myself we were able to get some great photos.  Here are just a few for your viewing pleasure.   And at the bottom of the page, you can click on the link to see blackmail photos for ARM, Synopsys, Cadence, Mentor Graphics, Breker, Oasys, Excellicon, Blue Pearl, LibTech, DeFacTo, Concept Eng, Tela, Oski Tech, Tanner, AMIQ, ClioSoft, Chip Path, Forte, Open Text, GlobalFoundries, Adapt IP, ThinkBold, Cayenne, and IBSystems (EDACafe).   Enjoy!

Feeling Good!

Read the rest of Photo Booth Blackmail!

Does SoC Sign-off Mean More Than RTL?

May 30th, 2013 by Graham Bell

This blog was first published in the System-Level Design Community of Chip Design Mag.

As the cost of failure continues to rise, SoC engineers see the growing importance of ensuring their work is as correct as possible as soon as possible in the design process. They cannot afford to carry errors forward from one stage to the next, where their impact grows while their causes become more obscured.

This requirement is driving the shift in design exploration and hand-off to the register transfer level. Using RTL for sign-off eases the integration of heterogeneous IP and makes it easier to check that the blocks are interfacing correctly with the host design, easier to check how clocks will cross these interfaces, and easier to check different power signatures and design testability. It also cuts the functional simulation load, especially when designs are being exercised at the system-level by reducing the number of states and the necessity to check for correct functionality.

What tools are available to improve the quality of RTL code before it reaches simulation and passes to synthesis? The latest generation of lint technology can handle full-chip designs of 500 million gates or more, and yet still can offer concise reporting. Timing constraints management and checking ensures correct timing for the block and full-chip level, so long as any changes in the RTL are reflected in the SDC files for the design. The SDC itself needs to be verified for correctness and consistency, and is essential for sign-off-grade analyses such as clock design crossing (CDC).

Read the rest of Does SoC Sign-off Mean More Than RTL?

Ascent Lint Rule of the Month: DEFPARAM

May 23rd, 2013 by Shiva Borzin, Technial Marketing Manager

This month we are going to look at the use of the  parameter statement in Verilog, which is used to define a constant local to a module.  References to a parameter are made by using its name.  A parameter can be redefined on an instance-by-instance basis in two different ways: parameter redefinition in the instantiation itself, or by using a defparam statement.

 Use of the defparam statement can easily cause confusion and trouble in the following ways:

·         Hierarchically changing the parameters of a module which may not be visible at the level of the affected module

·         Placing the statement in a separate file from the instance being modified

·         Using multiple statements in the same file to change the parameters of an instance

·         Using multiple statements in multiple different files to change the parameters of an instance

To avoid unintended constant redefinitions, some companies disallow the use of defparam statements in their design flows.   In the following example, the value of the parameter top.SIZE is changed at the very bottom level of hierarchy and may easily be missed. The designer may think that the SIZE and WIDTH parameters are still set to 8 as opposed to 4.

Read the rest of Ascent Lint Rule of the Month: DEFPARAM

Video: Gary Smith Tells Us Who and What to See at DAC 2013

May 23rd, 2013 by Graham Bell

Real Intent is again, this year, on Gary Smith’s writeup of “must see” products at DAC 2013 in the RTL Sign-off category.

I spoke with Gary Smith on Tuesday, May 21, to get his thoughts on who made the list and why, and other events at DAC you should know about… like the Denali Party.  The sound has some noise in it and I apologize for that.  Still the video is worth watching. Enjoy!

Be Early to Be Better

May 16th, 2013 by Graham Bell

Intel’s 10-core Westmere Processor

Today’s systems on chip (SoC) are deeply complex in new ways. A dozen or so years ago, a state-of-the-art processor such as the Intel Pentium 4 used 42 million transistors, was built on a 180nm process and relied upon discrete chips to handle its system interfaces. Scroll forward, and the Westmere processor that Intel introduced in 2012 uses 2.6 billion transistors and is built on a 32nm process. The chip includes ten 64bit x86 cores, L3 cache, graphics processing, DDR3 interfaces, virtualisation support and more. This trend to massive integration is even stronger in the mobile space, where SoCs bring together complex computing, communications and entertainment functions on one die.

It’s no longer possible to design all the subsystems of an SoC from scratch and expect to get the chip out in a reasonable timeframe, so today’s SoCs are complex integrations of new logic, IP blocks brought forward from previous designs, and functional and interface IP licensed in from third parties. Some companies are even using third-party IP to build their system interconnect, on the basis of that its communications management support and interfaces to other IP blocks will help get a design out more quickly. In effect, an SoC is a sea of interfaces.

Read the rest of Be Early to Be Better Gadfly — Real Intent’s not-so-secret DVcon’13 Report

May 9th, 2013 by Graham Bell

On May 9, 2013, John Cooley’s DeepChip site published a DVCon trip report we put together at Real Intent.  Here are some of the items covered:  Wally Rhine’s keynote, verification project stats, System Verilog, ad-hoc techniques, coverage and  power measurement, formal tools, UVM, CDC, Harry Foster, ARM, Intel, John Goodenough, Gary Smith, “AHA”, design breaking, no mention of C nor SystemC, Design to Help Verification, RTL, instrumenting, when to do formal?, assertion synthesis, no mention of Specman “e”, plus  details from Stu Sutherland’s talk on X-optimism, X-pessimism, the 15 X sources, how X’s mess each with constructs with assignments with operators, and three different ways to “fix” the X problem; plus the DVcon attendance numbers plus who exhibited there, too.

The report is quite long, and you can see it here or by scrolling the embedded frame below.  Enjoy!

Read the rest of Gadfly — Real Intent’s not-so-secret DVcon’13 Report

Unknown Sign-off and Reset Analysis

May 2nd, 2013 by Graham Bell

Elsewhere, Pranav Ashar, CTO at Real Intent, pointed out that the management of unknowns (X’s) in simulation has become a separate verification concern of signoff proportions. Modern power management schemes affect how designs are reset (start). X management and reset analysis are interrelated because many of the X’s in simulation come from uninitialized flip-flops and, conversely, the pitfalls of X’s in simulation compromise the ability to arrive at a clear understanding of the resetability of a design.

The SystemVerilog standard defines an X as an “unknown” value, which is used to represent when simulation cannot definitely resolve a signal to 1, 0, or Z. Synthesis, on the other hand, defines an X as a “don’t care,” enabling greater flexibility and optimization. Unfortunately, Verilog RTL simulation semantics often mask propagation of an unknown value by converting the unknown to a known, while gate-level simulations show additional X’s that will not exist in real hardware. The result is that bugs get masked in RTL simulation, and while they do show up at the gate level, time consuming iterations between simulation and synthesis are required to debug and resolve them. Resolving differences between gate and RTL simulation results is painful because synthesized logic is less familiar to the user, and X’s make correlation between the two harder. The verification engineer must first figure out whether the X in gate-level simulation is genuine before figuring out whether there is a bug in the design. Unnecessary X-propagation thus proves costly, causes painful debug, and sometimes allows functional bugs to slip through to silicon.

Continued increases in SOC integration and the interaction of blocks in various states of power management are exacerbating the X problem. In simulation, the X value is assigned to all memory elements by default. While hardware resets can be used to initialize registers to known values, resetting every flop or latch is not practical because of routing overhead. For synchronous resets, synthesis tools typically club these with data-path signals, thereby losing the distinction between X-free logic and X-prone logic. This in turn causes unwarranted X-propagation during the reset simulation phase. State-of-the-art low power designs have additional sources of Xs with the additional complexity that they manifest dynamically rather than only during chip power up.

Read the rest of Unknown Sign-off and Reset Analysis

Automatic RTL Verification: Find Bugs Before Simulation, May 2 Webinar

April 25th, 2013 by Graham Bell
Automatic RTL Verification with Ascent IIV: Find Bugs Before Simulation Real Intent Web-site
  Join us for a Webinar on May 2
Real Intent Products
Ascent Implied Intent Verification (IIV) is an early functional verification tool that provides immediate return on investment by quickly finding elusive bugs in RTL blocks. Ascent IIV can improve verification efficiency substantially and detect up to 50% of design functional errors prior to testbench development and simulation. Ascent IIV performs comprehensive verification using automatic check formulation followed by deep-sequential formal analysis.The webinar will introduce tool setup, the kinds of difficult bugs that can be found with the tool, and demonstration of its latest features.
Title: Automatic RTL Verification with Ascent IIV: Find Bugs Simulation Misses
Date: Thursday, May 2, 2013
Time: 10:00 AM – 11:00 AM PDT
After registering you will receive a confirmation email containing information about joining the Webinar.
Space is limited.
Reserve your Webinar seat now at:

Hear Alexander Graham Bell Speak from the 1880’s

April 25th, 2013 by Graham Bell

A dramatic application of digital technology has allowed researchers to recover Alexander Graham Bell’s voice from a recording held by the Smithsonian—a breakthrough announced for the first time. From the 1880s on, until his death in 1922, Bell gave an extensive collection of laboratory materials to the Smithsonian Institution, where he was a member of the Board of Regents. The donation included more than 400 discs and cylinders Bell used as he tried his hand at recording sound.  Bell today is credited with the invention of the phonograph record which replaced Edison’s cylinder recordings.

Click on the video link below to hear his voice, and read more about the sonic recovery at the Smithsonian Magazine web-site.

CST Webinar Series

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy