Open side-bar Menu
 Real Talk
Graham Bell
Graham Bell
Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »

Semi Design Technology & System Drivers Roadmap: Concluding Thoughts

 
December 19th, 2013 by Graham Bell

Andrew B. Kahng, Professor of CSE and ECE, Univ. of California at San Diego presented a paper on “The ITRS Design Technology and System Drivers Roadmap: Process and Status” at the 50th Design Automation Conference in Austin, TX.   This important review of the technology challenges that are in front of the EDA industry and what is the current status is presented here below in this final posting of a blog series.

7. CONCLUDING THOUGHTS

The Design Chapter in the ITRS has for well over a decade defined technology requirements and design challenges for the EDA industry and the VLSI CAD research community. Design technology roadmaps for DFM, low-power design, 3D/TSV integration, More Than Moore, etc. are continually added to maintain relevance of the roadmap. Recent Design Cost and Low-Power Design models highlight the challenges of design productivity, software design cost, and power management in future SOC and MPU designs. At the same time, the System Drivers Chapter has provided models for key market drivers as well as basic chip parameters (layout density, clock frequency, power dissipation, etc.) that bind the ITRS together via the Overall Roadmap Technology Characteristics. The MPU driver model has evolved frequency and power attributes in response to disappearing microarchitectural knobs, emergence of power limits, and challenges of device leakage; further changes (adding uncore elements, evolution of MPU-PCC for micro-server, updated die area modeling) are likely in the near future. The past decade has also seen increased reliance on “design-based equivalent scaling” (e.g., methods for activity factor reduction without compromising throughput or performance) to continue the semiconductor value proposition, and rapidly growing involvement in cross-TWG issues ranging from variability limits to device requirements.

The future of design technology roadmapping, and of the Design TWG’s work in the ITRS, will be affected by a variety of technical, business and cultural factors.

  • Past foundations of the ITRS seem increasingly shaky. For example, A-factors may no longer be constant across multiple technology nodes. Mx and poly pitches (i.e., horizontal vs. vertical densities) may scale at different rates. The fundamental assumption of 2× density scaling per node may be already long past; whether the industry can flourish with, e.g., 1.4× density scaling per node is an open question.
  • Tremendous uncertainty with respect to patterning technology (e.g., timing of EUV, directed self-assembly), cost models (e.g., triple- and quadruple-patterning), device and interconnect structures and properties (tunnel FETs, resistive RAMs, drive vs. leakage currents), and high-value applications all present challenges to the roadmapping of design technology requirements.
  • Fewer resources are available for ITRS activity even as the scope of the roadmap widens (MEMS, More Than Moore, new storage and switch elements, 3D integration) and the difficulty of the roadmapping task increases. Greater automation is needed to check consistency and impacts of proposed roadmap changes, a la the “Living ITRS” efforts of a decade ago [4].
  • An oligopolistic EDA industry, along with continued consolidation and disaggregation in the semiconductor industry, as well as unwillingness to share competitive (as opposed to pre-competitive) data, (see footnote 1) means that leading companies more frequently “opt out” of roadmap participation. There is a risk of a “vicious cycle” of decreased roadmap participation and decreased roadmap value.
  • Communication across supplier industries, across the design manufacturing interface, and across academia-industry boundaries is increasingly needed to optimize technology investments and maximize the returns from the roadmapping process. As the industry faces an explosion of post-CMOS, postoptical technology options, it seems appropriate to at least revisit the concept of “shared red bricks”.

Against this backdrop, there is some good news: Members of the design, EDA and research communities are willing to find common cause in the design technology roadmap. At the 2009 and 2010 EDA Roadmap Workshops [19], representatives from leading EDA companies, semiconductor companies, and research consortia commenced a dialogue to analyze needs and status of EDA roadmapping. See footnote 2. Other discussions sought new mechanisms by which more of the community could contribute to the design technology roadmap. And the really good news for EDA and VLSI CAD: If anything remains essential to the future of Moore’s Law scaling, it will be design technology, and design-based equivlent scaling.

Acknowledgments

Dr. Juan-Antonio Carballo has co-chaired the U.S. and International Design TWGs with me for the past decade, and has been particularly influential in the conception of the System Drivers Chapter as well as iNEMI and More Than Moore interactions. Dr. Kwangok Jeong developed and maintained the MPU, power, frequency and A-factor models during the critical years of 2007-2011, which saw many Design-PIDS interactions regarding roadmap for device power vs. performance. This paper would not exist without the help of UCSD Ph.D. students Tuck-Boon Chan, Siddhartha Nath, Wei-Ting Jonas Chan, and Ilgweon Kang. Many participants in the ITRS Design and System Drivers efforts, and in the overall ITRS effort, have contributed valuable insights and perspectives over the years. I also thank Dr. Sani Nassif (who has for years driven the DFM section of the Design Chapter) for organizing the special session which led to the writing of this paper.

Footnotes

  1. It is suboptimal for students at UCSD to “predict” designs and cell libraries that industry has already developed, or for students at Purdue to develop ab initio models for device structures that again have already been developed. Yet, these are the mechanisms by which core material and data is generated in the ITRS today.
  2. The 2009 workshop addressed such questions as “What would make an EDA roadmap more useful?”, “Which EDA areas lack most in roadmap efforts?”, and “Which EDA areas are behind what the roadmaps say?” The 2010 workshop then identified gaps in the EDA roadmap (system-level executable specification, designspace exploration and pathfinding, EDA scaling requirements in light of evolving computing platforms, power-driven design, and design for resilience), reached agreement on the nature of EDA, and identified challenges in filling in the EDA roadmap gaps (incremental design flows, new design for cost methodologies, and an expanded scope of EDA moving to system-level design).

References

[4] A. E. Caldwell, Y. Cao, A. B. Kahng, F. Koushanfar, H. Lu, I. L. Markov, M. R. Oliver, D. Stroobandt and D. Sylvester, “GTX: The MARCO GSRC Technology Exploration System”, Proc. DAC, 2000, pp. 693-698.

[19] EDA Roadmap Workshop at DAC 2010. http://vlsicad.ucsd.edu/EDARoadmapWorkshop/

Copyright Notice

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. DAC’13, May 29 – June 07 2013, Austin, TX, USA. Copyright 2013 ACM 978-1-4503-2071-9/13/05 …$15.00.

Q4 News, Year End Summary and New Videos

 
December 12th, 2013 by Graham Bell

Real Intent had an excellent Q4 and 2014!  Since our September newsletter we have announced a new release of Meridian Constraints (details below), another year of strong business growth, and seen many of you at trade shows in Silicon Valley, Japan, Israel, Germany and the United Kingdom.  In the December newsletter, learn about what the future holds, and how smart debug delivered better RTL verification.

To see the Q4 news, year end summary and the new videos click here.

Happy Holidays!

Semi Design Technology & System Drivers Roadmap: Part 6 – DFM

 
December 12th, 2013 by Graham Bell

Andrew B. Kahng, Professor of CSE and ECE, Univ. of California at San Diego presented a paper on “The ITRS Design Technology and System Drivers Roadmap: Process and Status” at the 50th Design Automation Conference in Austin, TX.   This important review of the technology challenges that are in front of the EDA industry and what is the current status is presented here below in this sixth part of a blog series.

6. DFM, VARIABILITY, RESILIENCE

Increasing process variability, mask cost, data size and lithography hardware limitations pose significant design challenges across different abstraction levels. The ITRS Design Chapter first introduced the design for manufacturing (DFM) section in 2005 to discuss DFM requirements and the corresponding solutions. DFM requirements can be broadly classified as (1) fundamental economic limitations, and (2) variability and lithography limitations. Requirements due to economic limitations focus on mask cost, which is a key limiter for SOC innovations coming from small companies and emerging-market entities. Requirements due to variability and lithography limitations include quantified bounds on the variability of supply voltage, threshold voltage, critical dimension, circuit performance and circuit power consumption.

Read the rest of Semi Design Technology & System Drivers Roadmap: Part 6 – DFM

The Future is More than “More than Moore”

 
December 5th, 2013 by Prakash Narain, President and CEO, Real Intent

As we approach the New Year, it’s a perfect time to think about the future – especially the future of verification. The “More than Moore” mindset that drives market demand for innovation in verification solutions has matured into more than “More than Moore,” due to much added complexity. All blocks now must work together. Dealing with multiple CPUs compounds the problem. You have to make sure CDC, SDC and power failure modes – all of which can happen concurrently – are identified earlier in your design process, to make it more predictable. Increased speed, capacity, and precision in digital verification intensify the need for best-in-class tools. In 2014 I think we’ll see more emphasis on using best-in-class verification solutions from startups. In contrast to larger companies, startups typically are focused on a particular area and can respond very quickly to every design request. That’s what we have found to be true at Real Intent. Our unsurpassed Meridian and Ascent verification tools help you innovate more quickly. No matter how adventurous and brilliant you are in your designs, you need tools that get you to sign-off, so all your ingenuity won’t come back to haunt you!

I would like to extend a personal thank-you to our customers for the very dynamic year we just completed at Real Intent. Working closely with you to address your needs, we added new capability to all of our products, and grew at a rate more than 10x that of the industry at large. I and the rest of the Real Intent team look forward to keeping pace with your innovation in the coming year. Very best wishes for a vibrant and prosperous 2014!

In the above video, I speak with Graham Bell about the accomplishments in the fiscal year 2013 ending on Oct. 31, the growth of our business by 60%, and to the market’s need for the speed, capacity and low-noise reporting of the company’s best-in-class solutions.

Customer Reports Results of Smarter RTL Verification

 
November 28th, 2013 by Graham Bell

I originally wrote and posted this blog here on SemiEngineering.com.  It is reproduced below.

SoC verification is gearing up for renewed competition among the big vendors and verification-only companies like Real Intent. They are delivering their next-generation SoC verification suites with a focus on specific areas of concern. Clock-domain crossing, X-verification and reset optimization, SDC correctness and consistency, are some of the areas that are receiving dedicated RTL analysis using static analysis. Static analysis is a mix of structural and formal techniques that let designers focus on verification and not on customizing the tool to attack a problem area.

Besides raw speed, and capacity, the newest tools are addressing the data management for sign-off of these SoCs. Smart reporting and assisted debug is a key requirement otherwise designers and verification teams will drown in a flood of analysis results. All of this innovation and targeted investment will be making SoC sign-off manageable, if not easier.

Recently, I saw the importance of having smart debug reporting in the results of an evaluation of Real Intent’s Ascent IIV tool by a customer in Japan. Read the rest of Customer Reports Results of Smarter RTL Verification

Experts at the Table: The Future of Verification – Part 3

 
November 21st, 2013 by Graham Bell

Ed Sperling, editor in chief of Semiconductor Engineering sat down with Prakash Narain, CEO of Real Intent, and other industry experts to discuss The Future of Verification.  In Part 3, presented here below, Narain discusses how validation-related attributes are rising up into the RT level.

Read the rest of Experts at the Table: The Future of Verification – Part 3

Experts at the Table: The Future of Verification – Part 2

 
November 18th, 2013 by Graham Bell

Ed Sperling, editor in chief of Semiconductor Engineering sat down with Prakash Narain, CEO of Real Intent, and other industry experts to discuss The Future of Verification.  In Part 2, presented here below, Narain considers how implementation issues are affecting functional verification.

Read the rest of Experts at the Table: The Future of Verification – Part 2

Experts At The Table: The Future Of Verification Part 1

 
November 14th, 2013 by Graham Bell

Ed Sperling, editor in chief of Semiconductor Engineering sat down with Prakash Narain, CEO of Real Intent, and other industry experts to discuss The Future of Verification.  In Part 1, presented here below, Narain explains why he is ” very happy that verification continues to be a problem.” Read the rest of Experts At The Table: The Future Of Verification Part 1

Video: Orange Roses, New Product Releases and Banner Business at ARM TechCon

 
November 7th, 2013 by Graham Bell

Real Intent was exhibiting at ARM TechCon on Oct. 30 – 31.  We gave away 100 orange roses at our booth in celebration of Halloween, and in anticipation of Diwali on Nov. 3.

Orange Roses Giveaway for ARM TechCon

Sanjay Gangal of Internet Business Systems interviewed me at the show as well.  In the following video, I spoke about the new releases of the Ascent Lint tool and the Ascent X-verification system and some hints about our upcoming business announcement for our fiscal year that just ended.  Enjoy. Read the rest of Video: Orange Roses, New Product Releases and Banner Business at ARM TechCon

Minimizing X-issues in Both Design and Verification

 
October 31st, 2013 by Lisa Piper, Senior Technical Marketing Manager at Real Intent

The propagation of unknown (X) states has become a more pressing issue with the move toward billion-gate SoC designs. The sheer complexity and the common use of complex power management schemes increase the likelihood of an unknown ‘X’ state in the design translating into a functional bug in the final chip.

This article describes a methodology that enables design and verification engineers to focus on the X states that represent a real risk, and to set aside those which are artifacts of the design process.

The idea is to reduce project time, particularly that spent in simulation, and overcome the limitations inherent in high-level techniques at both RTL and gate level. Read the rest of Minimizing X-issues in Both Design and Verification

CST Webinar Series
S2C: FPGA Base prototyping- Download white paper



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy