Lisa Piper, Senior Technical Marketing Manager at Real Intent
Lisa Piper is currently a Senior Technical Marketing Manager at Real Intent. She has extensive experience in simulation-based verification, acceleration and formal verification. Prior to Real Intent, Lisa worked at Lucent Microelectronics and AT&T Bell Labs. She has a BSEE from Purdue … More »
April 24th, 2014 by Lisa Piper, Senior Technical Marketing Manager at Real Intent
This article was originally published on TechDesignForums and is reproduced here by permission.
It’s an increasingly complex world in which we live and that seems to be doubly true of state-machine design.
With protocols such as USB3, PCI Express and a growing number of cache coherent multiprocessor on-chip buses and networks, the designer has been greeted with a state-space explosion. USB3 has, for example, added an entire link layer and, with it, the Link Training and Status State Machine. This is, in itself, a complex entity, which although it has only 12 states in total can move between them using a variety of different arcs. Read the rest of Complexity Drives Smart Reporting in RTL Verification
April 17th, 2014 by Graham Bell
I stopped in at EELive! show in San Jose on April 2, 2014 and spoke with Sanjay Gangal, President of Internet Business Systems and EDACafe.com about the latest release of the Ascent XV X-verification system and its latest design reset optimization features. I also gave a preview of the activities at the ChipEx conference in Israel on April 30, 2014 and the Design Automation Conference in San Francisco on the dates of June 2-4, 2014. Click on the picture to play the interview.
April 16th, 2014 by Graham Bell
The following is courtesy of the website XKCD.com and can be seen in its original form here: http://xkcd.com/1354
April 10th, 2014 by Graham Bell
Recently, we have seen announcements by the Big Three EDA Companies about new initiatives in the area of SoC verification. Synopsys for example, has started talking about Verification Compiler and how it is introducing static and formal checks for the first time, and relies on the Verdi debugging environment (acquired from SpringSoft) to tie it all together. Real Intent has been delivering solutions focused static and formal for several years now (and also relies on Verdi for Debug). The industry really started taking notice of this static verification trend in 2013 at DVCon and we have seen it grow through DAC 2013 in Austin. We are now talking about designs crossing the billion-gate threshold and what can be done to not only control this explosion of complexity, but also to achieve sign-off for RTL code.
RTL and gate-level simulation theoretically can be used to fully test a billion-gate SoC, but the cost of complete RTL testing is beyond what design teams can afford. To reduce the testing cost and the risk of missing critical tests, abstract modeling and pre-simulation static analysis of RTL have now become imperative in SoC design flows. Integration of heterogeneous IP and design units require confirmation of protocols, power budgets, testability and the correct operation of multiple interfaces and clock domain crossings (CDC).
April 3rd, 2014 by Ramesh Dewangan
I am old enough to recall the Pentium versus AMD processor rivalry of 1990’s. Back then, the chip complexity was all about number of transistors and clock speed. More and more complex Pentiums were reeling out of factory at a pace, faster than we replaced dress shirts in our closets!
In today’s SoC, complexity is not just about clock speed or number of transistors packed in tiny wafers. We don’t hear much about clock speed of processor in the Apple iPhone, or the Samsung Galaxy 4 smartphone, do we?
Are we building less complex chips? Have our applications become simpler?
Quite the opposite. Read the rest of Redefining Chip Complexity in the SoC Era
March 27th, 2014 by Graham Bell
The problem logic designers have with X’s is that RTL simulation is optimistic in behavior and this can hide real bugs in your design when you go to tapeout. Some engineers point out that we have always had to deal with X’s and nothing has really changed.
In fact, today’s SoC employ different power management schemes that wake-up or suspend IP. As any designer knows, when powering up logic, any X’s must be cleared on reset or within a specific short number of cycles afterword. The situation is now much more uncertain for designers whether all possible power scenarios are considered and all X’s will be cleared correctly.
Sorting all of this out with your simulator is too much and will be too late in the design process. So, the temptation is to supply a reset to all the flops in your design, but this will be costly in terms of precious routing density and power usage. Ideally, you would have a static tool that could analyze the rest scheme of your design and then suggest a minimum sub-set of flops that need reset lines. This week, on March 25, Real Intent unveiled major enhancements in its Ascent XV product for early detection and management of unknowns (X’s) in digital designs, which address this issue. Read the rest of X-Verification: A Critical Analysis for a Low-Power World (Video)
March 20th, 2014 by Graham Bell
Real Intent will exhibit its Ascent™ and Meridian™ products for advanced SoC sign-off at the SNUG® Designer Community Expo (DCE) – part of the Synopsys® Users Group (SNUG) Silicon Valley event March 24-26 – and also will make a presentation at the first Verdi Interoperable Apps (VIA) Developers Forum there. At the DCE, Real Intent will showcase its Meridian CDC and Ascent XV working with Synopsys’ industry-leading VCS® verification solution as a part of the IC Verification community. Real Intent’s Ascent products find elusive bugs and eliminate sources of uncertainty that are difficult to uncover using traditional Verilog or VHDL simulation, leading to both improved QoR and productivity of design teams. Meridian products accelerate sign-off verification of clock domain crossings and SDC in 500+M gate SoC designs.
At the VIA Developers Forum, myself and Mathew Yee, Sr. Application Engineer will present and highlight the features and benefits of Real Intent’s product integration with the comprehensive Verdi debug environment and its application to particular debug challenges such as clock domain crossing (CDC) verification. Read the rest of RTL SOC Verification Goes Better with Synopsys VCS and Verdi
March 13th, 2014 by Graham Bell
This blog was originally published in SemiEngineering.com and I wanted to make sure EDACafe readers saw it as well. I have also added some more content versus the original. Enjoy!
Previously I have blogged about the verification surveys that Real Intent runs at tradeshows throughout the year. We find it useful to track trends in tool needs and reveal what are the pain points designers are feeling. I last reported to you, a year ago, in the blog article Clocks and Bugs, where I focused on clock-domain crossing (CDC) errors causing re-spins.
This year, I would like to add some additional highlights and trends that I see from new survey data.
March 6th, 2014 by Graham Bell
February 27th, 2014 by Graham Bell
At last year’s Design and Verification Conference (DVCon) in San Jose, Real Intent sponsored a panel on “Where Does Design End and Verification Begin?” In this Part 3 we are continuing with the questions from the moderator and answers by the panelists.
The panel was moderated by Brian Hunter, Cavium, Inc. and panelists:
Pranav Ashar – Real Intent, Inc.
Below are links into the video recording where the question is asked and the immediate replies and comments by the panelists. Starting with Questions 15 the panelists shared several interesting insights about gaps with verification test-sets, and higher level modeling and had a lot of back and forth with the other members. Read the rest of DVCon Panel Drill Down: “Where Does Design End and Verification Begin?” – Part 3