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Your Real Intent Invitation to Fast Verification and Fun at DAC

Thursday, May 24th, 2012

Get Real at the 49th DAC!

You are invited to visit the Real Intent booth at the 49th DAC. Real Intent is known for having the fastest, high-capacity verification tools for early functional analysis including Lint, and for advanced timing sign-off of designs with multiple clock domains (CDC).

By completing our quick survey at the booth, you will be entered into drawings for cool tech-gadgets like a SlingBox PRO-HD or Kindle Fire, and for tickets to a Bay Area national sports team. There’s More! Enjoy a frosty bottled beverage on Monday or Tuesday afternoon and try your hand at our new Foosball table! You can look forward to both fast verification and fun times at this year’s DAC.

Our technical presentations will bring you up to date with our new product releases that came out in May. Click on the links below to book your appointment at the Real Intent booth #926.

New Ascent Lint 1.5.1 Release with Advanced Debugging and Faster Analysis

New Meridian Clock Domain Crossing (CDC) 4.1 Release with Advanced Features and Deeper Analysis

Ascent XV: Complete Solution for X Sign-Off Verification

Meridian Constraints: Comprehensive SDC Management and Verification

Ascent IIV: Automatic Detection of Functional Bugs Without a TestBench

See you at the show!


Thoughts on RTL Lint and a Poem

Monday, May 21st, 2012

The following blog entry was written by Jim Foley, R&D Director at Real Intent

Lately I’ve been thinking a lot about RTL lint.  This might be helpful to you, because if you’re tasked with solving multi-corner timing closure or characterizing activity for realistic power estimates, you know you don’t have much time left to think about lint.  Nor should you have to.  Granted, there are very many things that lint can check for – more about this in a bit — and there are as many different opinions about what constructs, conventions, and potential problems ought to be checked for and at which stage in the design process as there are individual design engineers.  I tend to put high value on lint rules that report on constructs that are legal but have suspicious modeling, that in Ascent Lint we categorize as “dubious”.  There’s also a lot of value to checking coding conventions to make code clear and readable – by whatever criteria meets that objective for you or your design group, as well as catching things that may simulate fine but may cost you time and trouble downstream in the design flow.


Video: Enter The DAC Zone

Thursday, May 17th, 2012

“You unlock this door with the Key of Imagination.”   Enter the DAC Zone with Sean ‘Serling’.


A Page is Turned

Thursday, May 3rd, 2012

Deciding on making a career change is always an interesting journey.   Most recently you probably knew me as ‘that guy who does the video interviews over at EDACAfe. ‘    You may not know that I have a history of  Corporate Marketing roles at several innovative EDA Companies such as Extreme DA and NASSDA (both of whom were acquired by SNPS) .

In April, I was having a meeting with Real Intent who are clients of EDACafe.  We talked about the promotion of their  market leading RTL Lint and Clock Domain Crossing analysis tools.  And then the discussion turned to a job opening in their Marketing team.   Very quickly we moved to negotiating my joining Real Intent in a full-time role as Sr. Director of Marketing, which is now official and took place on May 1.

I have enjoyed seeing the continuing dynamism and innovation in the EDA industry at and am now looking forward to being on the company side again.  To all of the EDACafe audience, I want to thank you for all the kind words and reception for the video interviews.  I look forward to seeing you at the DAC show in San Francisco in June.  Come by the Real Intent booth #926 and say hello.


+Graham Bell
Sr. Dir. of Marketing, Real Intent
tel: 408-830-0700 x222


Avoiding the Titanic-Sized Iceberg of Downton Abbey

Thursday, February 16th, 2012

Bugs have a way of turning up in an SoC design in the most inopportune time, much like the long-presumed dead relative and heir apparent who showed up recently at Downton Abbey, disfigured but hoping to be recognized.

While chaos may seem like a way of life for a verification engineer, in the PBS soap opera drama currently riveting the U.S. each Sunday evening, the Grantham family has been thrown into an unexpected state of chaos. Lord Grantham turned to a slew of lawyers to uncover the truth.  In our world, when a major bug is found, the manager of the verification group throws a slew of verification engineers at it who are often forced to deal with it through manual tests. And, that’s just the way it’s been.

On Downton Abbey, a survivor of the “unsinkable” Titanic arrives disfigured from an explosion during World War I, supposedly a relative of the Grantham Family declared dead six years earlier.  SoC functional verification challenges are big and complex and often resemble an iceberg that dwarfs the unprepared chip, not unlike the sinking of the Titanic.  Way too many verification teams sink after their SoC design hits an iceberg (or bug) of Titanic proportions.  That’s because they are using traditional methods, manually developing tests only able to address the tip of the verification iceberg. As a result, they often miss system functional and performance problems that aren’t apparent until first silicon. That verification manager ends up with a dilemma the size of Lord Grantham’s, though his or hers is related to time to market and the impact of revenue, and not the search for a male heir.

The solution for verifying an SoC is only now becoming clear since block-level testbench-based verification has been proven to be ineffective for SoC designs containing embedded processors. Complex SoC use cases that cross multiple concurrent applications with shared resources and on-board power and clocking management systems offer up an overwhelming number of possible scenarios.  Automation software can assess what to verify and rapidly generate test cases needed to adequately cover the wide spectrum of verification objectives.  Automated self-verifying C test cases running on embedded processors exercise a range of functional scenarios to ensure that the SoC can support concurrency, system-level and software functionality while meeting performance requirements.

The SoC verification problem is as daunting as the challenges facing Downton Abbey, though in today’s chip verification world, that it will be solved through automation.  We’re heading into DVCon later this month.  Expect to see a solution that automates the generation of portable self-verifying tests for multi-threaded SoC devices.  Visit the Breker Verification Systems exhibit at DVCon in booth #1002 to learn more.  While we can’t promise a visit from Lord Grantham or anyone else from Downton Abbey, we can offer something much more:  relief from the demands of SoC verification.

And, don’t miss our breakfast to be held from 7:30-8:30 a.m. Tuesday, February 28, during DVCon. It will include a panel discussion titled, “Do We Have What It Takes for Full-SoC Verification?” Open to all full DVCon conference and Tuesday conference-only registrants, it will be moderated by Brian Bailey of Brian Bailey Consulting and editor of EETimes’ EDA DesignLine.

Special thanks to the host of the Real Talk Blog, Real Intent. Don’t miss an opportunity to stop by its booth (#902) during DVCon to see demonstrations of Meridian and Ascent, software that accelerates Early Functional Verification and Advanced Sign-off of electronic designs. Real Intent Verification Expert Lisa Piper will present, “X-Propagation Woes: Masking Bugs at RTL and Unnecessary Debug at the Netlist,” at a Technical Program session on Formal Techniques Tuesday, February 28, at 11 a.m.

A Meaningful Present for the New Year

Tuesday, January 24th, 2012

Hope you all had a wonderful holiday season filled with happy memories, good food, and presents from your wish list!  At Real Intent, we welcomed two beautiful babies into our extended family during the holidays: Ryan Ayden Eram and Ebba Anthony Patterson! What better presents to keep us all motivated to work hard to improve the lives for our children!

As a new year present to the industry and our loyal customers, Real Intent announced the release of Meridian CDC version 4.0 on January 11. This release incorporates numerous enhancements and speedups. We will be covering many of the features in more detail in later blogs, but here are a couple of highlights:

  1. Real Intent’s Meridian CDC product has been the performance and capacity leader for some time now and the 4.0 release builds on the leadership with significant additional performance and capacity improvements (up to 5X) in structural analysis, design upload and GUI debug.  Meridian CDC 4.0 makes full chip CDC verification on 100+M gate SoC designs a reality and enables design managers to enforce full-chip CDC verification as a first-order sign-off requirement.
  2. Meridian CDC 4.0 makes it much easier and faster to setup the design environment (clock, reset, mode select, stable value, input and output domains through SDC translation and automatic design analysis) so that the time to the first useful CDC analysis is minimized. Our continuous efforts in this regard are testament to our customer-centric perspective. We truly believe that in addition basing our products on strong technology foundations, we must also ensure that we do our utmost to make our products the most usable.

Our existing customers are already benefiting from the speedup and added functionality in 4.0. Meridian CDC is the flagship product at Real Intent, and we have a clear focus and devote significant resources to keep it so. The team is already onto the next release target with even more exciting features and improvements to come.

As noted by Prakash Narain, CEO of Real Intent, “Meridian CDC 4.0 release represents a milestone in the industry for delivering a CDC verification solution that can be used to achieve complete CDC sign-off for large and complex SoC designs from RTL to gate.”

A Quick History of Clock Domain Crossing (CDC) Verification

Tuesday, August 2nd, 2011

The last decade has seen a sea change in integrated circuit design and verification. Around the year 2000, the Intel Pentium 4 had 42 Million transistors and was built on a 180 nm process, with CPU and interfaces built on different chips. A mere ten years later, Intel’s cloud server, Westmere EX, has 2.6 Billion transistors and was built on a 32nm process. It has 10 64-bit x86 CPUs, graphics, DDRs, virtualization, QPI, L3 Cache, a whole system on the same chip. It is mindboggling to think about the increase of complexity in IC design and verification in just a decade.

Electronic Design Automation (EDA) is a key enabler for the advance of IC/SoC designs. The advances in EDA tools parallel, as much as possible, the advances in IC design and verification. The development of Clock Domain Crossing (CDC) verification is a good example of this advancement.

In 2001, Cliff Cummings published a paper at SNUG called “Synthesis and Scripting Techniques for Designing Multi-asynchronous Clock Domains” ¹. In the paper, he talked about various asynchronous design techniques such as passing signals from fast to slow clock domains, passing multiple control signals, synchronizing datapaths by using handshakes and FIFOs. Cliff also proposed a CDC design methodology by adopting naming conventions and adhering to certain design partitioning principles.  In the paper, Cliff also discussed the impact of implementing asynchronous designs using synthesis and static timing analysis. Back then, Cliff was unaware of any CDC tools in the market. It was the era of simple CDC designs with less than 5 clock domains and manual review for CDC verification.

Things changed pretty quickly. In 2002, the first-generation CDC tools came to the market. Real Intent’s Verix CIV (Clock Intent Verification) was one of the pioneers in this field. The characteristic of the first generation tools was that they used structural analysis techniques to see if proper synchronization is in place and if there are unsafe CDC structures. While structural analysis alone was not sufficient to prove that all the asynchronous transfer protocols are safe, it was a step in the right direction and provided high value over manual review.

The second-generation CDC tools came around 2007, including Real Intent’s Meridian™ CDC.  These tools represented an advance in CDC verification technology by incorporating multiple verification techniques in addition to structural analysis. Formal analysis became an integral part of the solution in order to check for things such as data stability, pulse width, gray encoding and glitch potential. The tools also provided a simulation library and monitors so that users can perform CDC verification by injecting metastability effects during simulation and catching CDC violations using monitors. This advancement was necessitated by the number of bugs that slipped through to silicon due to clocking issues. According to Collett International and Farwest Research Group’s surveys conducted in 2002, 2004 and 2007, about 20% of chip re-spins were caused by clocking issues. As a result, functional CDC verification using formal analysis and simulation have become must-have techniques in the CDC verification flow.

Recognizing the change in CDC landscape, Cliff Cummings wrote a follow-up paper entitled “Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog” ², which won the 1st place award at SNUG 2008.  In this paper, Cliff provided a detailed discussion on problems and solutions in CDC design and verification, and in particular, he mentioned that the industry by then has identified these types of design techniques as clock domain crossing techniques. By 2008, CDC had become a known acronym in the industry and the problem space is also more or less well understood.

However well understood the problem may be, doesn’t mean it is completely solved. Advancement in design size and complexity has created additional requirements in CDC verification in recent years in the areas of performance and capacity. The second-generation tools, though functionally comprehensive, do not meet the needs of technology leaders who are designing multi-million-gate SoC designs with complex clocking architectures. To serve these companies, Real Intent released Meridian CDC 3.0 in 2010, with a focus on capacity and speed so as to enable CDC sign-off. With Meridian CDC 3.0, it is possible to verify over 100 Million gate flat full-chip designs with over 100 clock domains without having to break the design into smaller pieces for CDC verification. This translates into major productivity gains for the design team, and also eliminates the chance of bugs slipping through when stitching results together from sub-blocks. The ability to process a whole 100 Million gate design flat represents a significant improvement over earlier and other solutions.

The past 10 years have seen many changes in CDC design and verification. From a couple of asynchronous clock domains to well over 100 asynchronous clocks, from manual review to the 3rd generation CDC tools, and the trend is set to continue. Real Intent is a veteran and leader in the field of CDC verification, and will continue to serve the needs of design teams who are pushing the limit of today’s SoC designs as they approach one billion gates.


¹ Cliff Cummings, “Synthesis and Scripting Techniques for Designing Multi-asynchronous Clock Domains”,, SNUG-2001.

² Cliff Cummings, “Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog”,, SNUG-2008.

Hardware-Assisted Verification and the Animal Kingdom

Tuesday, July 26th, 2011

A senior executive of one of the big three EDA vendors was once quoted as saying:  “An emulator you used four years ago, you can use as a bookend, but not much else.  Or, you can throw it over the side of a boat and use it to grow coral.”

While we’ve chuckled over this comment for years, we think a better analogy comes from another part of the animal kingdom and it goes something like this:  Traditional hardware emulators are a lot like the dinosaurs that roamed the earth for 160 million years.  Both are now extinct, the latter wiped out at the end of the Mesozoic Era.  The former, wiped out by hardware-assisted verification platforms designed and implemented with the largest commercial FPGAs that are as fast and sleek as a Gazelle.

Dinosaurs were dominant terrestrial vertebrates, a term that sounds slow, plodding and ponderous, not at all unlike the description of early hardware emulators.

At their introduction in the 1980s, emulators were considered revolutionary and a bold feat of engineering marvel.  The high cost of ownership, however, limited adoption to big companies with large budgets and complex design problems.  Further, a traditional emulator’s maximum speed was about one megahertz (MHz), slow even then.  They were also criticized for being difficult to set up, wasting time and resources.  A common refrain in those early days was the excessive time to emulation.

Dinosaurs are known to have laid eggs.  Hmmm.

As we compare the latest generation of hardware emulation systems to the impressive gazelle, it’s easy to understand why they are changing designers’ perception of this market segment.  They perform at significantly faster speeds, are notably dexterous in their design verification deployment, and drastically more cost effective.

Gazelles are reputed to be swift animals.  In fact, some are able to maintain speeds as high as 50 miles per hour for extended periods of time.  Today’s emulation systems are equally swift –– some clock in at 10 megahertz (MHz) on a 40-million gate design.

These new functional verification engines have a small footprint and are light weight, saving space, power and infrastructure costs, and execute at speeds of several megahertz even in transaction-based co-emulation.  Their debugging capabilities are similar to those of the beloved HDL simulator.  Even more attractive is their pricing –– they sell for a fraction of the cost of older generations of emulators.  They can be used by the embedded software team and hardware designers for hardware/software co-verification, and increasingly are used as a solution to an event-based simulator’s runtime problems.

The gazelle is appreciated for being both nimble and graceful, and does not lay eggs.

Experts tell us we can learn much from the Animal Kingdom.  We’ve learned enough to be able to compare and contrast the characteristics of chip verification tools to two venerated animals.  As we’ve shown, traditional emulators have gone the way of the Dinosaur while today’s fast emulation systems are emulating the characteristics of a Gazelle.

Advanced Sign-off…It’s Trending!

Wednesday, July 13th, 2011

DAC. Whether you love it or not, it is a fantastic opportunity to have quality meetings with design and verification engineers from all over the world. No other event brings so many engineers and engineering managers to one place, where important new trends, technologies, challenges and solutions can be discussed and debated.

With double-digit increases in attendance in all categories, DAC 2011 in San Diego was a success. Floor traffic was high, our suites were booked, conversations with designers were productive, and the iPad drawing prizes were flying off the shelves in every booth!

DAC doesn’t just represent an opportunity to tell attendees what solutions we have to offer. More importantly, it is a great opportunity to learn from designers and verification engineers what they think is important, what trends they are noticing, and what they are looking toward in the future.

While much of this discussion in anecdotal, one useful way we gather trend data at Real Intent is through our attendee survey form. Hundreds of visitors to the Real Intent booth completed a survey to report their challenges, attitudes toward different topics, and what keeps them up at night. By aggregating this data we can see some important trends.

One new question we collected data for was the attendees’ plans to adopt RTL Sign-off Technologies. (Note that in this graph, the numbers are absolute, not percentages).

Adoption Plans for Verification Technologies

As you can see, many people are already using Lint and CDC tools, although these areas are still growing as they are being driven by design complexity. The newer applications of Constraint Verification and X-Propagation Analysis showed less current usage, and relative to that, significant interest in adoption. In fact, X-Verification in general was one of the hottest topics at DAC this year, with many visitors to our booth inquiring about our new solution, Ascent™ XV.

Another important question we ask attendees is about the number of clock domains they expect in their next design. I’ll show this as a pie graph, and number of responses to this question was 163.

Number of Clock Domains

Compared to previous surveys we have done, the number of clock domains keeps going up, with two-thirds of respondents expecting more than 25, and a significant number expecting more than 100. This trend is obviously driving the strong demand we are seeing for our flagship product, Meridian™ CDC.

While on the subject of CDC, we asked DAC attendees if they have ever had a CDC bug slip through, causing a late-stage ECO or silicon re-spin.

CDC Bugs Slipping Through

There were 94 responses to this question, with nearly two-thirds reporting that they have had a CDC bug slip through. With the complexity of SoCs increasing, as evidenced by number of clock domains, this is clearly fueling more need for CDC Verification tools like Meridian CDC.

It’s not surprising then, to see the answer to the next question: Do you Consider CDC Verification to be a Sign-off Criterion?

Is CDC a Sign-off Criterion?

With 103 responses, an overwhelming majority, 83% of attendees, see CDC Verification as a necessary addition to their sign-off regimen, since CDC bugs cannot be detected by functional simulation or static-timing analysis.

We also surveyed attendees on the issues that they encounter with their current CDC or Lint tool. As we expected, the problem of noisy reports ranks high. This is primarily because the industry-leading Lint tool, and its add-on CDC option, relies on templates and does not ensure a correct design environment set-up. Without a correct set-up, many non-issues are erroneously flagged, resulting in a noisy report with actual CDC bugs being lost in a sea of tens of thousands of warning messages.

Issues with CDC or Lint Tools

Ranking even higher, interestingly, was performance. As SoC designs grow larger, full-chip CDC analysis becomes intractable for all but the fastest and highest-capacity tools. This is an area where Meridian CDC shines, routinely handling designs in excess of 100 Million gates.

Shifting gears to one of the newest and hottest topics at DAC, we asked attendees about their level of concern about functional bugs that are caused by differences in X-Interpretation, and found that it is quite high.

Concern About X Bugs

While X-Propagation hazards are not a new problem, they are growing in significance thanks to increasing design complexity. Not only can X-Propagation problems mask functional bugs in RTL simulation, but they also require painful debugging of mismatches between RTL and gate-level simulation. Out of the 118 responses to this question, only 13% of attendees registered no concern, and a full quarter were “very concerned”. Indeed, the interest level in Ascent XV, Real Intent’s new solution for X-Verification, was extremely high at DAC.

Finally, we asked about the area of Exceptions and Constraints Management, to learn what “pain points” attendees were dealing with.

Pain Points in Exceptions and Constraints Management

Constraints Checking was easily the highest reported “pain point”, with other areas related to constraints and exceptions also being ranked highly. This is clearly an important and growing problem that requires modern tools, such as Real Intent’s PureTime™, to address constraints and exceptions management across full-chip SoC designs.

In summary, DAC offered Real Intent an opportunity to not only tell attendees about our solutions, but to measure the important trends and concerns that designers face today, as well as report them back to you.

I would like to thank every DAC attendee that completed our survey form. To give them even more reason to participate, each attendee who completed the survey was entered into a drawing for an iPad 2. I am happy to announce that the winner of the iPad 2 drawing was Jim Kelly of NVIDIA. Congratulations, Jim!

We look forward to seeing you next year at DAC 2012 in San Francisco!

Learn about Advanced Sign-off Verification at DAC 2011

Tuesday, May 24th, 2011

If you are coming to DAC 2011 in San Diego, June 6th through 8th, you’ll want to make sure you visit Real Intent in booth #2131 to learn about the latest technology for Advanced Sign-off Verification.

Real Intent will feature its Ascent™ XV solution, the industry’s first and only solution for comprehensive X-verification and sign-off. Ascent XV isolates and eliminates functional bugs that are masked by X (unknown value) propagation in RTL simulation, and reduces gate-level simulation debugging due to mismatches between RTL and gate-level simulation results caused by differing X interpretation.

Also to be featured are the latest advances in Meridian™ CDC, the industry’s flagship Clock Domain Crossing sign-off verification solution, and new capabilities within Ascent Lint, the industry’s fastest and most accurate lint solution, which is complemented by automatic formal checks in Ascent IIV (Implied Intent Verification).

Real Intent will also show Meridian DFT, its Design-for-Test verification solution, and PureTime™, its constraints management solution with glitch-aware exception verification.

And, to learn what solutions will be crucial to verifying the billion-gate designs that are right around the corner, be sure to hear Real Intent CEO Prakash Narain along with other experts from Intel, Broadcom, NVIDIA, Qualcomm and Mindspeed on the DAC technical panel entitled:

“The Billion Dollar Question: How to Verify Billion-Gate Designs”

Wednesday, June 8, 2011 – 4:00 PM to 6:00 PM – Room 33ABC – For details, Click here

Next-generation chips will contain literally billions of gates that need to be verified before committing to silicon. With billions of dollars at stake, the right solution is crucial for verifying designs susceptible to complex failures arising from corner-case confluences of timing and functionality. This panel will debate the merits of emerging solutions for such self-contained verification problems that threaten to subvert the nominal “simulation plus STA” verification flow.


If you’d like to learn how to comprehensively sign-off on your RTL code for X-accuracy, CDC integrity, syntax, semantics, DFT and constraints integrity, then please be sure to book your private meeting with Real Intent’s experts by visiting  Appointments are available Monday through Wednesday, 9 AM to 6 PM, but slots are limited, so register TODAY!


  • Please visit booth #2131 at DAC 2011
  • Complete a short survey at the booth to enter our drawing!

We look forward to seeing you at the show!

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