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When to Retool the Front-End Design Flow?

Thursday, August 30th, 2012

The following blog entry was written by Rick Eram, Director of Field and Sales Operations at Real Intent

I work with many design teams who are trying to find an optimal time point for updating and retooling their front-end design flow.  The decision is not as easy as you might think.  The various managers I meet struggle with this question, since it requires careful analysis of the existing flow, identifying any bottlenecks, and a detailed understanding of the current engineering design cost compared to a replacement toolset.  Managers also have to understand the team interactions around the world, their deliverables and responsibilities, and how designers work within each functional group.  And the switching cost must be quantified in hard numbers.

In the back-end world of circuit netlists and layouts, the decision to retool is simpler since the move to a new silicon technology node typically dictates when to change.  The benefits are obvious and much easier to quantify.  Metrics for run time, capacity, accuracy, and ease of achieving timing closure makes the job of understanding and analyzing the cost of current versus new tools much simpler to understand, quantify, and justify.  If these performance metrics in the current tool-set are degrading significantly because of greater design complexity, and the impact of multiple operating modes and statistical effects, the design team will not be successful.  A change is clearly needed.

So, how does a manager determine when to retool the front-end design flow and maximize efficiency?  Are current tools costing way too much of engineering time and not as efficient as they once were?  What is the real switching cost?  And what about the impact on verification?  Since verification is more and more intertwined with actual RTL design, a decision about a tool change must take that into account. (more…)

Verification challenges require surgical precision

Thursday, August 23rd, 2012

Pranav Ashar, CTO at Real Intent, discusses how verification challenges require more than simulation and timing analysis.

Design companies have continued to buy functional verification tools through the recent downturn and the prediction is that verification spending will continue to rise. While this is good news for EDA companies, it is also an indicator of the industry’s challenge in containing the verification problem as design complexity continues to rise in terms of the number of transistors and the system-level functionality on a chip.

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How To Article: Verifying complex clock and reset regimes in modern chips

Thursday, August 16th, 2012

The following was originally published in EDN as an IC Design Center How-To article on Jan. 25, 2011.   It provides a thorough treatment of verifying complex clock and reset regimes, including examples of silicon re-spins caused by clock and reset related failures, and the necessary scalable solutions to sign-off a design. (more…)

X-Verification: What Happens When Unknowns Propagate Through Your Design

Thursday, August 9th, 2012

This article is an update to Lisa Pipers original posting from April 2011: X-verification: Conquering the “Unknown”

SoCs today are highly integrated, employing many disparate types of IP, running at different clock rates with different power requirements. Understanding the new failure modes that arise from confluences of all these complications, as well as how to prevent them and achieve sign-off, is important. While the issue of handling “X’s” in verification has always been there, it has become more exasperated by low power applications that routinely turn off sections of chips, generating “unknowns”.

Lisa introduces the topic of X-Verification in her DVCon 2012 video interview:

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Video: “Issues and Struggles in SOC Design Verification”, Dr. Roger Hughes

Thursday, August 2nd, 2012

Dr. Roger Hughes, Sr. Application Engineer at Real Intent speaks with Graham Bell about the current verification challenges for complex SOCs.  This interview took place at the Real Intent DAC 2012 booth in early June.

Roger is a renowned international expert in formal verification technologies and has over 20 years experience in the EDA industry working both at start-up companies in lead engineering roles and publicly traded companies in managing and directing technical product development. He obtained his Electronic Engineering degree at University of Wales, Swansea and his Masters in Digital Systems and his Ph.D in Electronic Engineering at Brunel University, UK. He has published over 70 papers. (more…)

Video: What is Driving Lint Usage in Complex SOCs?

Thursday, July 26th, 2012

A lint tool is a design and coding guideline checker for HDL code and confirms that  it is ‘clean’ and ready for the design tool chain.  The rules used in a lint tool capture years of experience and typically come from industry standards such as the Reuse Methodology Manual (RMM), and the IP reuse guidelines from STARC.

Besides helping to enforce some appropriate naming schemes, they evaluate design and coding deficiencies that impact simulation, synthesis, test, performance and RTL/gate-level sign-off.  Some of the common RTL lint rules include:

  • Unsynthesizable constructs
  • Unintentional latches
  • Unused declarations
  • Multiply driven and undriven signals
  • Race conditions
  • Incorrect usage of blocking and non-blocking assignments
  • Incomplete assignments in subroutines
  • Case statement style issues
  • Set and reset conflicts
  • Out of range indexing

(more…)

How is Verification Complexity Changing, and What is the Impact on Sign-off?

Thursday, July 19th, 2012

I had the pleasure of speaking with Pranav Ashar, CTO at Real Intent, in the recorded video below, about how verification complexity is changing in new designs and how that is impacting design sign-off.

Dr. Ashar makes it clear scale complexity is not going away.  High-end SOCs today, easily go beyond 100M logic gates and we will see further CMOS silicon technology-shrinks, so bigger designs are forthcoming.  With the adoption of the SOC paradigm however, chips have evolved into true systems with diverse components integrated together into one design.

The elephant in the in the room that design teams are now realizing, is that the tremendous effort to create designs with aggressive performance and power goals has consequences for verification.   There are now first-order requirements that are not met by the nominal functional verification and timing analysis flows.

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Foosball, Frosty Beverages and Accelerating Verification Sign-off

Thursday, July 12th, 2012

In this video interview, I talk about the two recent press announcements that just came out about new product releases and growing business momentum, and the fun we were having at the Real Intent booth at DAC in San Francisco, June 4-6.

Here you can see the Foosball table in action:

A Good Design Tool Needs a Great Beginning

Tuesday, July 3rd, 2012

The following blog entry was written by Rick Eram, Director of Field and Sales Operations at Real Intent

Designing an excellent EDA tool takes a great deal of understanding from several different viewpoints.  First the tool designers must understand the actual engineering problem they are trying to solve.  Second, they must understand the end-user design needs and satisfy those in the tool.  Third the results have to be meaningful and consistent with the user’s existing design flow and ideally do not make it harder for designs to be signed off by engineers and their managers.

Software developers spend years refining their products to meet market demands.  The first solution out of the box usually gets the need part right, but can miss on the meaningfulness of the results and presentation of information, as well as ease of use. For example, one of the RTL linting solutions in the marketplace started out as a generic checker over 10 years ago.  A decade later, many hours of unnecessary debugging time is lost every day the tool is invoked because of the overhead due to checking and waiving erroneous messages.  The reason for this misalignment of the customer needs lies solely on the way the tool was designed from the start.

(more…)

Video Preview of Real Intent Presentations at DAC

Thursday, May 31st, 2012

Prakash Narain, CEO of Real Intent, talks about the two recent press announcements that just came out about new product releases and growing business momentum, and what you will see if you come by the Real Intent booth #926 at DAC in San Francisco, June 4-6.

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