Archive for the ‘Uncategorized’ Category
Thursday, October 17th, 2013
I had the pleasure to attend the EDA: Back to the Future event at the Computer History Museum last night. There were over 230 guests to raise money for the EDA Oral History Project at the Museum. There were industry luminaries honored at the event, and I did red carpet interviews with many of them as they arrived including Joe Costello, Simon Segars, and Penny Herscher. If you would like to know more about the Museum project watch this very cool video that was shown to the attendees:
You can make a gift donation to the Computer History Museum in support of the EDA Oral History Project by following the link here.
Monday, October 14th, 2013
Brian Bailey, Engineering Consultant & EETimes DesignLine contributing editor, recently did an in-depth interview of Prakash Narain, CEO of Real Intent about his career in EDA. In this last of a four part blog series, Prakash talks about listening, SoC sign-off and the Internet of Things.
Thursday, October 10th, 2013
Brian Bailey, Engineering Consultant & EETimes DesignLine contributing editor, recently did an in-depth interview of Prakash Narain, CEO of Real Intent about his career in EDA. In this third of a four part blog series, Prakash reveals why Real Intent changed its focus, the role of static verification and if there are any regrets.
Monday, October 7th, 2013
Brian Bailey, Engineering Consultant & EETimes DesignLine contributing editor, recently did an in-depth interview of Prakash Narain, CEO of Real Intent about his career in EDA. In this second of a four part blog series, Prakash reveals why he has grey hair, the role of mentors and that the company’s first product was an accidental discovery.
Thursday, October 3rd, 2013
Brian Bailey, Engineering Consultant & EETimes DesignLine contributing editor, recently did an in-depth interview of Prakash Narain, CEO of Real Intent about his career in EDA. In this first of a four part blog series, Prakash confesses how EDA is complex, fascinating, and intellectually satisfying but at the same time a little painful.
Thursday, September 26th, 2013
Three weeks ago, I shared a video interview of Pranav Ashar talking about how SoC Sign-off Needs Analysis and Optimization of Design Initialization in the Presence of Xs. Last week Real Intent announced the latest release of its Ascent XV that address this new sign-off concern.
Analysis and optimization of design initialization in the presence of X’s is a new requirement for SoC sign-off due to modern power-management schemes. Ascent XV provides the necessary analysis of initialization sequences to ensure they are complete and optimal for various power states in an SoC. It provides the same best-in-class verification performance and debug efficiency as our other Ascent products, uncovering issues prior to digital simulation and synthesis.
Ascent XV identifies X-sources and potential X-propagation issues early-on in Verilog RTL or netlist designs. It enables the detection and debug of functional issues caused by X-optimism at RTL, prior to synthesis. It also eliminates unnecessary X’s caused by X-pessimism at the netlist. Ascent XV analysis can catch issues prior to RTL sign-off, driving costs down and avoiding monotonous, error-prone debug at the netlist level.
Thursday, September 19th, 2013
This blog was originally published on TechDesignForums and can be read here.
In early summer, Real Intent was among companies at the forefront of promoting a more unified approach to RTL sign-off, unveiling a deal that linked its market-leading Meridian CDC clock domain crossing suite to design-for-test tools from DeFacTo Technologies. Now though, as president and CEO Prakash Narain explains, the company is focusing on the broader concept of SoC sign-off.
“Take CDC as an example,” explains Narain. “You cannot sign off on CDC purely at the RTL because it is very possible that synthesis will introduce problems that cause your design to fail. So, you need the capability to run a small part of the CDC verification on your netlist as well.
“We provide that with Meridian and that is why we see ourselves as an SoC sign-off company. You are often looking at things that cannot be done at just the RTL level.”
Thursday, September 12th, 2013
On Sept. 12, Real Intent, announced significant enhancements for our Ascent Lint product, which we claim is the industry’s fastest and most accurate tool RTL lint Analyzer and rule checker. It handles 500M gate designs in just minutes and so it is easy to find errors prior to Verilog or VHDL simulation, leading to improved quality of results (QoR) and higher design team productivity.
The new 2013 version of Ascent Lint delivers enhanced support for SystemVerilog, Verilog and VHDL languages, and improves ease of use in the GUI and low-noise reporting of design issues. A new integrated Emacs-mode feature enables users to view and manage all lint violations at each RTL source location for easier debugging. Users now can edit the source code, manage violations, and rerun Ascent Lint to view updated violations – all from within the Emacs editor.
Further notable enhancements and new features for Ascent Lint include:
- 22 new lint rules that ensure design code quality and consistency for a wide range of potential issues
- A new CDC Readiness policy to ensure that the design is ready for Clock Domain Crossing analysis
- Extension of regular expression syntax to be Perl-compatible for more flexible processing
- Enhanced RTL analysis, processing and selection of source and library files
- Comparison of separate analysis reports to expose differences and changes
For more information about the new enhancements for Ascent Lint 2013, please watch this short (3 minute) video by Shiva Borzin, Technical Marketing Manager at Real Intent. (more…)
Thursday, September 5th, 2013
For today’s SoCs, modern power management schemes affect how designs are reset (started). X management and reset analysis are interrelated because many of the X’s in simulation come from uninitialized flip-flops and, conversely, the pitfalls of X’s in simulation compromise the ability to arrive at a clear understanding of the resetability of a design.
In the video interview below, Pranav Ashar, CTO at Real Intent, points out how verification sign-off now must include analysis of reset and design initialization to ensure it is correct and optimal for various power modes in an SoC.
Thursday, August 29th, 2013
Andrew B. Kahng, Professor of CSE and ECE, Univ. of California at San Diego presented a paper on “The ITRS Design Technology and System Drivers Roadmap: Process and Status” at the 50th Design Automation Conference in Austin, TX. This important review of the technology challenges that are in front of the EDA industry and what is the current status is presented here below in this fifth part of a blog series.
5. LOW-POWER DESIGN
In response to power and energy being identiﬁed as the grand challenge for the semiconductor roadmap, the Design TWG in 2011 added a Low-Power Design technology roadmap to the Design Chapter. The low-power design roadmap contains a mix of future solutions spanning electrical, functional and software realms . Projected low-power design innovations include (i) frequency islands and near-threshold computing at the circuit level; (ii) heterogeneous parallel processing, many core software development tools, and hardware/software co-partitioning at the architecture level; and (iii) power-aware software and software virtual prototyping at the software level. Figure 8 shows that with low-power innovations the SOC-CP driver dissipates 3.5W (with 48.8M logic gates) in 2011. Low-power design innovations will help limit the power to 8.22W when the number of logic gates grows by more than 40x to 1995.5M in 2026.