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Steve McQueen’s Mustang Explains Net Neutrality — Thursday, Aug. 21

Tuesday, August 19th, 2014

I became aware of the following Panel discussion taking place on Thursday, Aug. 21 in Palo Alto CA, and thought it would be of interest to the EDACafe audience.

Net Neutrality is all but certain to influence the patterns of data communication. Irrespective of its outcome, the viability of underlying infrastructure and economics is still an evolving discussion.

In this panel, the philosophical value chain of Net Neutrality is explored. As consumers, it is imperative on us to inspect the scalability of such policies towards our future requirements. For which, the flow of data across Content Delivery Networks, Wired and Wireless Operators, and Service Providers are critical to be understood. Conceptualizing a value chain and its components provides context for studying the broader impact. Essentially, fairness and value are what individuals, entrepreneurs and enterprises seek in sustaining the growing demands of data usage.

The goal of this event is hence in peeling back the layers of technology, usability and regulatory standards to better understand the fundamental forces at play.

For a quick background on the topic, watch Steve McQueen’s Mustang Explains Net Neutrality. (more…)

Fundamentals of Clock Domain Crossing Verification: Part Four

Thursday, July 31st, 2014

Last time we discussed practical considerations for designing CDC interfaces.  In this posting, we look at the costs associated with debugging and sign-off verification.

Design setup cost

Design setup starts with importing the design. With the increasing complexity of SOCs, designs include RTL and netlist blocks in a Verilog and VHDL mixed-language environment. In addition, functional setup is required for good quality of verification. A typical SOC has multiple modes of operation characterized by clocking schemes, reset sequences and mode controls. Functional setup requires the design to be set up in functionally valid modes for verification, by proper identification of clocks, resets and mode select pins. Bad setup can lead to poor quality of verification results.

Given the management complexity for the multitude of design tasks, it is highly desirable that there be a large overlap between setup requirements for different flows. For example, design compilation can be accomplished by processing the existing simulation scripts. Also, there is a large overlap between the functional setup requirements for CDC and that for static timing analysis. Hence, STA setup, based upon Synopsys Design Constraints (SDCs), can be leveraged for cost-effective functional setup.

Design constraints are usually either requirements or properties in your design. You use constraints to ensure that your design meets its performance goals and pin assignment requirements. Traditionally these are timing constraints but can include power, synthesis, and clocking. (more…)

Fundamentals of Clock Domain Crossing Verification: Part Three

Thursday, July 24th, 2014

Last time we looked at design principles and the design of CDC interfaces.  In this posting, we will look at practical considerations for designing CDC interfaces.

Verifying CDC interfaces

A typical SOC is made up of a large number of CDC interfaces. From the discussion above, CDC verification can be accomplished by executing the following steps in order:

  • Identification of CDC signals.
  • Classification of CDC signals as control and data.
  • Hazard/ glitch robustness of control signals.
  • Verification of single signal transition (gray coding) of control signals.
  • Verification of control stability (pulse-width requirement).
  • Verification of MCP operation (stability) of data signals.

All verification processes are iterative and achieve design quality by iteratively identifying design errors, debugging and fixing errors and re-running verification until no more errors are detected.

(more…)

Fundamentals of Clock Domain Crossing Verification: Part Two

Thursday, July 17th, 2014

Last time we looked at how metastability is unavoidable and the nature of the clock domain crossing (CDC) problem.   This time we will look at design principles.

CDC design principles

Because metastability is unavoidable in CDC designs, the robust design of CDC interfaces is required to follow some strict design principles.

Metastability can be contained with “synchronizers” that prevent metastability effects from propagating into the design. Figure 9 shows the configuration of a double-flop synchronizer which minimizes the load on the metastable flop. The single fan-out protects against loss of correlation because the metastable signal does not fan out to multiple flops. The probability that metastability will last longer than time t is governed by the following equation:

Eqn1

(more…)

Fundamentals of Clock Domain Crossing Verification: Part One

Thursday, July 10th, 2014

The increase in SOC designs is leading to the extensive use of asynchronous clock domains. The clock-domain-crossing (CDC) interfaces are required to follow strict design principles for reliable operation. Also, verification of proper CDC design is not possible using standard simulation and static timing-analysis (STA) techniques. As a result, CDC-verification tools have become essential in design flows.

A good understanding of the CDC problem requires an understanding of metastability and the associated design challenge.

Metastability

When the input signal to a data latch changes within the setup-and-hold window around the transition of the latching clock, the latch output can become metastable at an intermediate voltage between logical zero and one. Figure 1 shows a simplified latch implementation. The metastable state is a very high-energy state as shown in Figure 2. Because of noise in the chip environment, this metastable voltage gets disturbed and eventually resolves to a logical value. The resolution time is dependent upon the load on the latch output and the gain through the feedback loop. It is impossible, however, to predict this logical value. Also, there is an inherent delay in the resolution of the metastable output as shown in the timing diagram of Figure 3. This logical and timing uncertainty introduces unreliable behavior in the design and, without proper protection, can cause it to fail in unpredictable ways.

 

Fig1
Figure 1. A simplified latch.

(more…)

Photo Booth Blackmail at DAC in San Francisco!

Thursday, June 12th, 2014

Real Intent had a photo booth at its exhibit in San Francisco at the Design Automation Conference.  We thought it would be cool to give a photo souvenir of the 51st conference for anyone who strolled by and to celebrate the 2014 FIFA World Cup.  On hand to work the booth was Jeremy who helped everyone with funny props or choosing the right World Cup team jersey.

Between Jeremy and myself we were able to get some great photos.  Here are just a few for your viewing pleasure.   And at the bottom of the page, you can click on the link to see all the blackmail photos for your fellow conference attendees and exhibitors.   Enjoy!

Happy Patriot!

(more…)

Quick Reprise of DAC 2014

Thursday, June 5th, 2014

Thanks to everyone that came to the 2014 Design Automation Conference.  It was a successful show with maximum traffic on Tuesday afternoon.  At the Real Intent booth we were giving away Roses (yes they were real!) and had a photo booth as well.   Visitors could dress up in world-cup soccer jerseys and hoist the World Cup 2014 Trophy.

IMG_0316 (more…)

Fun and Fast RTL Sign-off at DAC in San Francisco

Wednesday, May 28th, 2014

Real Intent is bringing lots of valuable information and fun to the Design Automation Conference (DAC) 2014 in San Francisco June 2-4, 2014, at Booth #1825:

  • Technical presentations about its new product releases proven on 500M+ gate SoC designs.
    • New Ascent Lint 2014 with blazing speed for debugging – The industry’s fastest linter for cleaning RTL now has 46+ new comprehensive rules; it analyzes 500M gates in less than one hour with no need for hierarchical processing, and features debugging with the Emacs editor, hierarchical waiver management, SystemVerilog 2009 support, and new integration with MATLAB® from Mathworks.
    • Meridian Clock Domain Crossing with advanced flows and debug features - It offers market-leading speed, capacity and low-noise analysis of asynchronous clock domains in SoC designs, and improves the memory footprint and runtime performance by almost one-third.
    • Ascent XV comprehensive static solution for the latest in X-propagation verification, reporting and debug  – Its unique ability to seamlessly integrate techniques of simulation, static analysis and formal analysis into a unified flow maximizes coverage and minimizes user burden to achieve X safety. It ensures that simulation performance and accuracy are not impacted by X-effects; it precisely identifies all X-sources and X-sensitive nets, and ranks which nets to analyze first; it identifies uninitialized flops and suggests a minimal number of hardware resets for complete initialization with minimal RTL changes; and it provides initialization and optimization capability for power-managed blocks to ensure that the combination of resets and retention flops establish a known state.
    • Ascent IIV: Automatic detection of functional bugs without a test bench - Leveraging formal techniques for functional verification, it uses the implied RTL intent to formulate checks automatically, find elusive bugs in RTL blocks and pinpoint the root cause of the problem. Its smart reporting prioritizes debug effort by marking up to 90-percent of the failures as secondary or duplicate, reducing the time spent on analysis. The new 2014 release minimizes debug time with enhanced root cause analysis, smarter reporting and new FSM checks — shrinking the debug signoff burden to almost nothing for a very large amount of checks.
  • Other technical presentations
    • How to accelerate RTL sign-off of SoC designs with a best-in-class solution – It covers a full suite of static verification concerns including syntax and semantic checking (lint); constraints planning and management; reset analysis and optimization; automatic intent verification; CDC sign-off; DFT analysis and insertion; and X-analysis and optimism/pessimism correction.
    • Joint Meridian CDC and Defacto STAR DFT Flow – First-time showing of a combined RTL sign-off flow for both CDC and DFT that accelerates the sign-off process. The new flow integrates Defacto’s STAR DFT evaluation and enhancement platform, and Real Intent’s Meridian CDC to offer a best-in-class solution for SoC design teams worldwide.
  • Pavilion panel organizer: “The Asymptote of Verification” – Bryon Moyer, editor of EE Journal will moderate the discussion as panelists from Cavium, Infineon Technologies AG and NVIDIA talk about bringing a higher level of automation, predictability, and ROI to system-on-chip (SoC) functional verification, based on their real experiences with formal verification, static RTL analysis and graph-based verification technologies.
  • Passport Partner program – Visit Real Intent industry partners Calypto, Defacto and MathWorks that share joint flows with Real Intent, and enter to win several $100 gift cards or a 10-inch Android tablet.
  • Verification survey at the booth – Enter drawings for a Pebble Smartwatch, Google Chromecast, or Golden State Warriors tickets.
  • Video game - To celebrate the 2014 FIFA World Cup Brazil, come and play as the captain of your country’s team.
  • Free photo booth – Get an entertaining take-away for you and your colleagues.
  • Roses give-away - Come and receive yours as a sweet thank-you gift for our visitors.

Click here to see a very informative five-minute video by Real Intent President & CEO Prakash Narain. In it he references Real Intent’s mission to make RTL signoff more efficient and previews four products it will highlight at DAC 2014 that advance the state of the art.

Next Generation of Static RTL Sign-off

Thursday, May 22nd, 2014

Years ago when Real Intent began, 10 million logic gate designs were considered “top of the line.” Today you might be dealing with billion-gate designs – significantly more complicated across a far wider scope of applications. The sheer complexity leads to a whole new host of verification challenges. Because sign-off is an iterative process, you have to deal with things like capacity, performance, power and timing issues, and engineering effort at each step. There’s a real need for toolsets that handle functional verification tasks prior to simulation and synthesis to avoid the exorbitant cost of silicon failure – so much so, that even Synopsys is getting onboard with a new verification suite.

Real Intent is committed to deliver the industry’s best possible software tools for verifying next-generation digital designs for FPGAs and complex SoCs. Our Ascent products for static functional verification prior to synthesis, and our Meridian products for advanced sign-off verification for CDC and constraints timing, uniquely address specific SoC sign-off issues. They save design and verification engineers a lot of time and effort, and give 10x better design quality and productivity compared to alternative methods. We also work closely with industry leaders like Defacto, Calypto and our newest industry partner, MathWorks, to ensure quality and compatibility.

(more…)

Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog Assertions

Thursday, May 1st, 2014

Its only one month left until the Design Automation Conference in San Francisco,  June 1-5 and the process of getting ready is keeping me BUSY.   This week, I would like to highlight the DVCon 2014 Best Oral Presentation by Kelly D. Larson from NVIDIA on “Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog Assertions.

This paper describes an entirely different way to use these same SVA assertions. While the standard use of SystemVerilog assertions is typically targeted towards DESIGN QUALITY, this paper describes how to effectively use assertions to target individual TEST QUALITY. In many cases the same SystemVerilog assertions which were written for measuring design quality can also be used to measure test quality, but it’s important to realize that the fundamental goal is quite different. (more…)

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