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Google Designing Its Own Next-Generation Smartphone SoCs?

Thursday, November 5th, 2015

Courtesy Ron Amadeo and Intel

Google is starting to push to have more say in the design and architecture of the chips that run the Android system in smart phones.  They are also apparently making major investments into virtual reality, where some of the chip design effort is expected. And hiring staff from major SoC companies.

Ron Amadeo from the tech publication Ars Technica has published the following online report:  According to a pair of reports from The Information (subscription required), Google has big ambitions for the inside of Android phones. The report says the search giant has sent a long list of requests to chip manufacturers for future SoC designs and that Google is even planning to build its own processors.

The report says that during discussions that happened this fall, “Google representatives put forward designs of chips it was interested in co-developing, including a phone’s main processor.” The new chips are reportedly needed for future Android features that Google hopes to release “in the next few years.” By designing its own chips, Google can make sure the right amount of horsepower gets assigned to all the right places and remove bottlenecks that would slow down these new features.

The report specifically calls out “virtual and augmented reality” as use cases for the new chips. Publicly, only Google Cardboard has surfaced from Google’s VR initiative, but internally, it seems like the company is gearing up for a huge VR push. Some of Google’s biggest names have left their posts on flagship products to go work on the virtual reality team: Jon Wiley, the lead designer of Google Search, and Alex Faaborg, the former lead designer for Firefox, Google Now, and Android Wear. An earlier report from The Wall Street Journal claimed Google was building a version of Android that would become a virtual reality operating system.

Read the rest of Ron Amadeo’s article here and learn who Google is hiring.

DAC Verification Survey: What’s Hot and What’s Not

Thursday, October 15th, 2015

At the Design Automation Conference in San Francisco, Real Intent did a survey of 201 visitors to our booth.  We focused on RTL and gate-level verification issues.  Below is a brief introduction and you can see the entire survey on the DeepChip.com web-site.


DAC’15 “When is your next design start?”

0-3 months : ########################################### (52%)
3-6 months : ###################### (26%)
6-12 months: ################## (22%)

These numbers are very similar to what was reported in 2012 on DeepChip. With half of the future design starts occurring in the next 3 months, this leads me to think design activity is remaining strong despite any EDA user consolidation we might have seen with the big mergers of various chip companies, and the slowing of the Chinese economy. However, the latest IC forecast from Gartner has 2015 growth falling from 5.4% at the beginning of 2015 down to 2.2% in July.
(more…)

On-the-Fly Hardware Accurate Simulation, New Meridian CDC, ASICON Tutorial

Thursday, October 8th, 2015

In this blog, we are presenting the highlights from Real Intent’s Fall 2015 Verification Newsletter. First are some thoughts from Prakash Narain, CEO, followed by an introduction to the new 2015 release of Meridian CDC for clock-domain and reset-domain crossing sign-off, and finally a review of our fall events including an ASICON tutorial.

Thoughts From Prakash Narain, President and CEO…

Most functional verification for SoC and FPGA designs is done prior to RTL hand-off to digital synthesis, since gate-level simulations take longer to complete and are significantly harder to debug.  However, gate-level simulations are still needed to verify some circuit behavior.  Unfortunately, X’s in gate-level simulations can cause differences in the RTL simulation output and the gate-level simulation output.  X’s generally exist in all designs – it can be difficult to prevent this for practical reasons.  Simulation results may be different because of X’s that are hidden in the RTL simulation by X-optimism, or additional X’s may exist due to X-pessimism in gate-level simulations. Pessimism can be fixed by overriding the simulator because you know that real hardware would always resolve to a deterministic value. The challenge is confirming that the X value is a result of X-pessimism and not simply X-propagation, and then forcing it to the right value at the right point in time so the simulation matches that of real hardware.

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Calypto Design Systems: A Changed Partner

Thursday, September 17th, 2015

Calypto Design Systems was embraced by Mentor Graphics this week.  Founded in 2002, the company was born out of discussions between founder Devadas Varma and Dado Banatao, partner at Tallwood Venture Capital.  By early 2005, it had raised $22 million in venture capital, and had 42 employees, 18 with PhDs.  It was tackling equivalence checking (SLEC) between ESL and RTL design representations.

In 2011, Mentor bought a 51% interest in the company and sold Calypto its Catapult-C synthesis technology, which seemed like a good match to their SLEC tool.  With Calypto’s growing success, it was natural that Mentor would pull them into their fold.

For several years, Calypto Design Systems and Real Intent have co-operated in support of verification flows for mutual customers.  Both companies shared the same distributor is Korea.

One flow we had jointly announced was our Ascent Lint with their Catapult synthesizer.  Catapult lets designers use industry standard ANSI C++ or SystemC to describe functional intent at the ESL level. From these high-level descriptions, Catapult automatically generates production quality RTL.  Ascent Lint ensures Catapult-generated RTL code is lint clean and error free for a safe and reliable implementation flow from RTL to GDSII layout.
(more…)

Thunderbolt 3 and USB Type-C: the 40 Gbps + 100W Answer

Thursday, September 10th, 2015

As the computer, tablet and smartphone industries move toward adoption of the new USB Type-C connector, a new version of Thunderbolt is quickly approaching. With speeds topping 40 gigabits per second, Thunderbolt 3 promises to provide another solution to unify various display, docking, power, storage and network protocols currently available under the USB Type-C standard, with data transmission speeds beyond that of USB Type-C as well as other protocols like DisplayPort and PCI Express.

USB and Thunderbolt have been widely used to connect various peripheral devices providing storage, display, and recently, power capabilities though distinct ports on devices. And until now, these ports have been separate. When work by Intel began on the Thunderbolt 3 interface, the port was going to continue to be unique until standards began to emerge for USB Type-C.

A USB Type-C connector.

USB Type-C connector

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Good news! The Next Big Thing in Verification is Already Here.

Thursday, August 20th, 2015

The Wilson Research Group 2014 functional verification study exposes many interesting trends in the techniques used and troubles seen by both designers and verification engineers.  Harry Foster of Mentor Graphics has been been blogging about the study for some time now.

As I was looking over the report slides, there was an interest trend that stood out for me.

Figure 1. The Mean Time that Design Engineers spend doing design versus doing verification.

(more…)

A Verification Standard for Design Reliability

Thursday, August 13th, 2015

_do-254The great thing about a standard is that once you decide to use it, your life as a designer is suddenly easier.  Using a standard reduces the long list of choices and decisions that need to be made to get a working product out the door.  It also gives assurance to the customer that you are following best practices of the industry.

A standard for the world of aviation electronics (avionics) is the RTCA/DO-254, Design Assurance Guidance For Airborne Electronic Hardware.  It is a process assurance flow for civilian aerospace design of complex electronic hardware typically implemented using ASICs or big FPGAs.  In the USA, the Federal Aviation Administration (FAA) requires that the DO-254 process is followed.  In Europe there is an equivalent standard called EUROCAE ED-80.

At first glance the standard seems daunting. It defines how design and verification flows must be strongly tied to both implementation and traceability. In DO-254 projects, HDL coding standards must be documented, and any project code must be reviewed to ensure it follows these standards.  They address the following issues: (more…)

New 3D XPoint Fast Memory a Big Deal for Big Data

Thursday, August 6th, 2015

After years of research, a new memory technology emerges that combines the best attributes of DRAM and NAND, promising to “completely evolve how it’s used in computing.”

Memory and storage technologies such as DRAM and NAND have been around for decades, with their original implementations able to perform only at a fraction of the level achieved by today’s latest products. But those performance gains, like most in computing, are typically evolutionary, with each generation incrementally faster and more cost effective than the one preceding it. Quantum leaps in performance often come from completely new or radically different ways of solving a particular problem. The 3D XPoint technology announced by Intel in partnership with Micron comes from the latter approach.

The initial technology stores 128Gb per die across two memory layers.

“This has no predecessor and there was nothing to base it on,” said Al Fazio, Intel senior fellow and director of Memory Technology Development.  “It’s new materials, new process architecture, new design, new testing. We’re going into some existing applications, but it’s really intended to completely evolve how it’s used in computing.”

Touted as the biggest memory breakthrough since the introduction of NAND in 1989, 3D XPoint is a new memory technology that is non-volatile like NAND memory, but is up to 1,000 times faster, with a faster speed only attainable by DRAM, and with endurance up to 1,000 times better than NAND. (more…)

Video: SoC Requirements and “Big Data” are Driving CDC Verification

Thursday, July 23rd, 2015

Just before the design automation conference in June, I interviewed Sarath Kirihennedige and asked him about the drivers for clock-domain crossing (CDC) verification of highly integrated SoC designs, and the requirements for handling the “big data” that this analysis produces.  He discusses these trends and how the 2015 release of Meridian CDC from Real Intent meets this challenge.

He does this in under 5 minutes!   You can see it right here…

50th Anniversary of Moore’s Law: What If He Got it Wrong?

Thursday, July 16th, 2015
Electronics Mag Cover Aug, 1965

Electronics  April 16, 1965

On April 19, 1965, Electronics magazine published an article that would change the world. It was authored by a Fairchild Semiconductor’s R&D director, who made the observation that transistors would decrease in cost and increase in performance at an exponential rate. The article predicted the personal computer and mobile communications. The author’s name was Gordon Moore and the seminal observation was later dubbed “Moore’s Law.” Three years later he would co-found Intel. The law defines the trajectory of the semiconductor industry, with profound consequences that have touched every aspect of our lives.

The period is sometimes quoted as 18 months because of Intel executive David House, who in 1975 predicted that chip performance would double every 18 months; being a combination of the effect of more transistors and their faster switching time.

What if Gordon Moore got his math wrong and that instead of the number of components on an integrated circuit doubling every couple of years, he said every three years? (more…)

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