I had just learned this week that my mentor into the world of EDA, Dr. Miles Copeland had passed away recently.
At Carleton University in Ottawa, Canada, Copeland was the former chair of the Department of Electronics and Professor Emeritus in the Faculty of Engineering and Design. He was an IEEE Fellow and was known for his passion for teaching and research innovation.
In addition to educating two and a half generations of electrical engineers, Copeland had established Carleton’s research capacity in the area of analog and radio frequency integrated circuit design, including the development of computing techniques to enable and reinforce research and learning.
The focus on computing techniques was how I came to work with Copeland. (more…)
There were a number of announcements at DAC 2016 in Austin concerning SDC timing constraints verification and management. Real Intent announced the newest release of Meridian Constraints for sign-off of SoC designs. It features new and unique functional analysis, data-driven debug, and support for distributed design development.
In this blog, I want to cover the drivers for a new kind of Constraints verification tool.
Constraints Management today is clearly different from the pre-SOC and pre-IP eras. The design process is now truly distributed with much legacy and third-party IP in any new SOC design. This implies that the SDC creation process must go through the three steps of (a) aggregation from the component SDCs to an overall SoC-level SDC, (b) refinement of the SoC-level SDC, and (c) dis-aggregation of the SoC-level SDC into SDCs for the synthesis partitions. The key point here being that the synthesis-partition boundaries need not align with the logical boundaries of the component IPs. (more…)
At the front of the Speakeasy was Killer Tofu, Boston’s premier 90’s band, rockin’ the tunes and getting everyone dancing.
At the back of the venue was Sri Saripalle of Random Designs CA Inc. and his 3-D scanner. He was doing whole body scans so you could get a 4 inch-high figure as a memento of the event. Of course, getting the 3D print of myself isn’t free, but I think the charge is quite reasonable.
Here he is the preview of the scan. The password in GB_DAC16 Click and drag to change the orientation. Do you think it looks like me? I will update this blog when I get my hard-copy. (more…)
Real Intent is bringing its advanced Ascent and Meridian technology, EDA expertise and espresso energy to the 53rd Design Automation Conference (DAC) in Austin, Texas, June 5-9, 2016. Before I mention the BEST DAC parties, Real Intent invites attendees to Booth #527 to:
Learn the latest information about Real Intent’s Ascent family of tools for the fastest static RTL verification prior to synthesis and simulation, and its Meridian tools that enable CDC and SDC sign-off at the RTL and gate-level.
View technical presentations to get up to speed on Real Intent’s latest advancements, proven on giga-gate SoC and FPGA designs. Click here to make an appointment for one of our private suite presentations:
How to Accelerate Your RTL Sign-off
Ascent Lint with New Visualization and VHDL 2008
Meridian CDC with New Analysis and Data-driven Flow
Ascent XV with Advanced Gate-level Pessimism Analysis
Case Studies in Physical CDC Analysis for Gate-Level Sign-off
New Next-Generation Constraints Exception Verification
Complete a quick verification survey to be entered into drawings for a cool Roku 4 streaming player and an Amazon Echo wireless speaker and voice commander.
Espresso Yourself and enjoy a high-speed coffee from our DeLonghi Magnifica super-automatic coffee machine, to celebrate faster verification and design.
Visit Real Intent and OpenText (Booth #638), Real Intent’s “Espresso Yourself” partner at DAC; get a ticket stamped by both companies to enter drawings to win $100 Amazon Gift Cards.
John Cooley’s Deepchip.com web-site likes to publish end-user experience with various EDA tools. On May 6, he published a posting on why a designer switched from Atrenta SpyGlass to Real Intent for CDC, Lint, and X-propagation analysis. His report details the reasons for converting to our best-in-class tool suite.
Here is the first part of the posting:
We had been using SpyGlass from Atrenta, and it worked OK for us, but we
were told by our local Real Intent sales guy that “there would be fewer
iterations for Lint, easier setup for CDC, lower-noise reporting, and
faster runtimes” — if only we evaled his tools.
REAL INTENT MERIDIAN CDC VS. ATRENTA SPYGLASS CDC
I spent one work week (5 days) evaluating Meridian CDC. We used different
designs to evaluate this tool. The first was 850K gate design that had
3 asynchronous clock domains. For the analysis setup, Meridian CDC
automatically detected all the clock/reset candidates correctly at block-
level as well as the top-level. No additions were needed for the setup
file, while our Spyglass run did require manual editing of the setup.
The Meridian runtime for this block was ~5 minutes.
The second design was 4 million gates and had 5 asynchronous clock domains.
Again the automatic clock/reset detection worked as expected. The runtime
was ~15 minutes.
Read the rest of the report on CDC, lint and X-propagation here.
Have you switched EDA tools recently? How was that experience?
More than Moore – Enabling the Power of System Scaling:
An Open Discussion About Design and Manufacturing Challenges
Join the ESD Alliance on the evening of May 17th at 6PMwhen we will be hosting an open dialogue about system scaling solutions and what it will take to propel them into the mainstream for semiconductor design and manufacturing. Although various system scaling technologies (such as interposer-based designs, using die-level IP blocks, like HBM) are already in use today, they have not yet crossed into the mainstream.
System scaling offers an excellent alternative path to pursuing Moore’s Law by moving the integration focus from the transistor to the integration of several heterogeneous pre-fabricated and proven devices, in the form of die-level IP, into an advanced IC package. Although new sub- 10nm process technologies continue to drive Moore’s Law, development cost and times at these advanced nodes are beyond the reach of much of the mainstream market.
It will take collaboration and cooperation between modeling, design, analysis/verification, manufacturing and test in order to unlock the potential of these new integration solutions. The objective for the meeting is to have an open discussion to identify the highest priority issues that should be jointly worked on to streamline the path to widespread adoption. The ESD Alliance is in the process of forming a working group representing both manufacturing and design to work on practical solutions and is seeking community input on direction and priorities.
This is an open event and we encourage anyone who is involved with or interested in system scaling from either the design or manufacturing perspective to attend. Please join us at 6 pm for networking, food and beverages prior to the open discussion forum, starting at 6:30.
Recently I came upon an article by Ankush Sethi of Freescale on the importance of avoiding bad design practices that lead to glitches in clocks which result in asynchronous behavior. He points out:
It is very important to make digital designs free of any clock or data glitches to ensure correct functioning. There are many cases where such issues have caused functional failure, or increased design time through incurring extra debug effort. Hence, it is very important for a designer to take care of such issues at the earliest stages of design once flagged by a tool or gate-level synthesis.
With the increasing complexity of SoCs, multiple and independent clocks are essential in the design. The design specifications require system level muxing of some of these clocks before they are sent to actual IP. Also, to save power, clock gating cells are inserted in clock paths. While implementing these muxing and gating cells, a designer tends to make mistakes that can lead to glitches. A glitch on a clock signal exposes a chip (or a section of a chip) to asynchronous behavior. A glitch-prone clock signal driving a flip-flop, memory, or latch may result in incorrect, unstable data. This paper discusses structural faults that can lead to glitches in clocks. Also, some bad design practices that lead to glitches in data are discussed. (more…)
Please join Silicon Valley verification and design engineers on April 27, 2016 at Dave and Buster’s in Milpitas for a catered lunch, networking, and presentation by Cliff Cummings. This is a no charge event.
What are virtual sequencers and virtualssequences and when should they be used? Tests that require coordinated generation of stimulus using multiple driving agents benefit from using virtual sequences. This presentation will clarify important concepts and usage techniques related to virtual sequencers and virtual sequences that are not well documented in existing UVM reference materials. This presentation will also detail the m_sequencer and p_sequencer handles and the macros and methods that are used with these handles. The objective of this presentation is to simplify the understanding of virtual sequencers, virtual sequences and how they work. (more…)
Pranav Ashar, CTO at Real Intent was interviewed in April by SemIsrael, Israel’s leading semiconductor design and development portal, on the latest trends in the world of verification. Below, I have embedded video clips that cover each of the five questions he addressed. You can watch the entire video here.
Q1. What is the current trend driving verification?
At DVCon’16, Mark Litterick presented a paper and presentation on “Full Flow Clock Domain Crossing – From Source to Si.” Here is the abstract for the paper:
Functional verification of clock domain crossing (CDC) signals is normally concluded on a register-transfer level (RTL) representation of the design. However, physical design implementation during the back-end pre-silicon stages of the flow, which turns the RTL into an optimized gate-level representation, can interfere with synchronizer operation or compromise the effectiveness of the synchronizers by eroding the mean time between failures (MTBF). This paper aims to enhance cross-discipline awareness by providing a comprehensive explanation of the problems that can arise in the physical implementation stages including a detailed analysis of timing intent for common synchronizer circuits.
Mark works for Verilab as senior verification consultant and holds the position of fellow. He is based in Munich, Germany. To see more of Mark’s technical papers, check out his profile page on the Verilab web-site.
Even though, you may have signed-off for CDC at RTL, logic synthesis, design-for-test and low-power optimization tools can break CDC at the gate-level, the physical implementation stage of design. Real Intent’s Meridian products provide clock-domain crossing verification and sign-off. Our most recent offering is Meridian Physical CDC and provides sign-off at the netlist level of the design. It uses a mix of structural and formal methods to identify glitching and other errors that break the correct registration of signals crossing clock domains. (more…)