Lisa Piper, Senior Technical Marketing Manager at Real Intent
Lisa Piper is currently a Senior Technical Marketing Manager at Real Intent. She has extensive experience in simulation-based verification, acceleration and formal verification. Prior to Real Intent, Lisa worked at Lucent Microelectronics and AT&T Bell Labs. She has a BSEE from Purdue … More »
June 30th, 2016 by Lisa Piper, Senior Technical Marketing Manager at Real Intent
Most functional verification is done before the RTL is handed off for digital synthesis. Gate-level simulations take longer and are hard to debug, but still needed to verify some circuit behavior. Ideally, the output of the RTL simulation will match the output of gate-level netlist simulation after synthesis. But that is not typically the case. Besides the obvious things verified in your gate-level simulations, there are always unknown values (Xs). Some will not be seen in the RTL due to X-optimism, but there will be additional Xs in the gate-level simulations due to X-pessimism.
X-optimism in RTL and other generic issues around unknown states are discussed in more detail in the paper ‘X-Propagation Woes – A Condensed Primer‘. Some basic familiarity with the concept is assumed here.
This paper focuses on X-pessimism at the netlist level. It discusses some current techniques and their limitations, and then describes a more efficient X-pessimism strategy based on Real Intent’s Ascent XV. Read the rest of Fix X-pessimism in Netlists with Practical Techniques
June 30th, 2016 by Graham Bell
At Carleton University in Ottawa, Canada, Copeland was the former chair of the Department of Electronics and Professor Emeritus in the Faculty of Engineering and Design. He was an IEEE Fellow and was known for his passion for teaching and research innovation.
In addition to educating two and a half generations of electrical engineers, Copeland had established Carleton’s research capacity in the area of analog and radio frequency integrated circuit design, including the development of computing techniques to enable and reinforce research and learning.
The focus on computing techniques was how I came to work with Copeland. Read the rest of In Memory of Dr. Miles Copeland: Innovator and Mentor
June 16th, 2016 by Graham Bell
There were a number of announcements at DAC 2016 in Austin concerning SDC timing constraints verification and management. Real Intent announced the newest release of Meridian Constraints for sign-off of SoC designs. It features new and unique functional analysis, data-driven debug, and support for distributed design development.
In this blog, I want to cover the drivers for a new kind of Constraints verification tool.
Constraints Management today is clearly different from the pre-SOC and pre-IP eras. The design process is now truly distributed with much legacy and third-party IP in any new SOC design. This implies that the SDC creation process must go through the three steps of (a) aggregation from the component SDCs to an overall SoC-level SDC, (b) refinement of the SoC-level SDC, and (c) dis-aggregation of the SoC-level SDC into SDCs for the synthesis partitions. The key point here being that the synthesis-partition boundaries need not align with the logical boundaries of the component IPs. Read the rest of How SoC Design is Driving Constraints Management and Verification
June 16th, 2016 by Graham Bell
The night of Monday June 6 in Austin was the awesome Heart of Technology (HOT) party and fundraiser for CASA of Travis County that was hosted by Jim Hogan and lots of sponsoring companies that were at DAC.
At the front of the Speakeasy was Killer Tofu, Boston’s premier 90’s band, rockin’ the tunes and getting everyone dancing.
At the back of the venue was Sri Saripalle of Random Designs CA Inc. and his 3-D scanner. He was doing whole body scans so you could get a 4 inch-high figure as a memento of the event. Of course, getting the 3D print of myself isn’t free, but I think the charge is quite reasonable.
Here he is the preview of the scan. The password in GB_DAC16 Click and drag to change the orientation. Do you think it looks like me? I will update this blog when I get my hard-copy. Read the rest of HOT Party at DAC in 3D
May 26th, 2016 by Graham Bell
Real Intent is bringing its advanced Ascent and Meridian technology, EDA expertise and espresso energy to the 53rd Design Automation Conference (DAC) in Austin, Texas, June 5-9, 2016. Before I mention the BEST DAC parties, Real Intent invites attendees to Booth #527 to:
May 12th, 2016 by Graham Bell
John Cooley’s Deepchip.com web-site likes to publish end-user experience with various EDA tools. On May 6, he published a posting on why a designer switched from Atrenta SpyGlass to Real Intent for CDC, Lint, and X-propagation analysis. His report details the reasons for converting to our best-in-class tool suite.
Here is the first part of the posting:
We had been using SpyGlass from Atrenta, and it worked OK for us, but we
REAL INTENT MERIDIAN CDC VS. ATRENTA SPYGLASS CDC
I spent one work week (5 days) evaluating Meridian CDC. We used different
The second design was 4 million gates and had 5 asynchronous clock domains.
Read the rest of the report on CDC, lint and X-propagation here.
Have you switched EDA tools recently? How was that experience?
May 12th, 2016 by Graham Bell
April 28th, 2016 by Graham Bell
It is very important to make digital designs free of any clock or data glitches to ensure correct functioning. There are many cases where such issues have caused functional failure, or increased design time through incurring extra debug effort. Hence, it is very important for a designer to take care of such issues at the earliest stages of design once flagged by a tool or gate-level synthesis.
Here is his introduction followed by an iframe of the article from EDN magazine.
With the increasing complexity of SoCs, multiple and independent clocks are essential in the design. The design specifications require system level muxing of some of these clocks before they are sent to actual IP. Also, to save power, clock gating cells are inserted in clock paths. While implementing these muxing and gating cells, a designer tends to make mistakes that can lead to glitches. A glitch on a clock signal exposes a chip (or a section of a chip) to asynchronous behavior. A glitch-prone clock signal driving a flip-flop, memory, or latch may result in incorrect, unstable data. This paper discusses structural faults that can lead to glitches in clocks. Also, some bad design practices that lead to glitches in data are discussed. Read the rest of 7 Design Faults Leading to Clock and Data Glitches
April 21st, 2016 by Graham Bell
Please join Silicon Valley verification and design engineers on April 27, 2016 at Dave and Buster’s in Milpitas for a catered lunch, networking, and presentation by Cliff Cummings. This is a no charge event.
11:30am: Doors Open / Networking
12:00pm: Lunch / Presentation
“Using UVM Virtual Sequencers & Virtual Sequences”
What are virtual sequencers and virtualssequences and when should they be used? Tests that require coordinated generation of stimulus using multiple driving agents benefit from using virtual sequences. This presentation will clarify important concepts and usage techniques related to virtual sequencers and virtual sequences that are not well documented in existing UVM reference materials. This presentation will also detail the m_sequencer and p_sequencer handles and the macros and methods that are used with these handles. The objective of this presentation is to simplify the understanding of virtual sequencers, virtual sequences and how they work. Read the rest of DVClub Silicon Valley: “Using UVM Virtual Sequencers & Virtual Sequences”, Wed. Apr. 27
April 14th, 2016 by Graham Bell
Pranav Ashar, CTO at Real Intent was interviewed in April by SemIsrael, Israel’s leading semiconductor design and development portal, on the latest trends in the world of verification. Below, I have embedded video clips that cover each of the five questions he addressed. You can watch the entire video here.
Q1. What is the current trend driving verification?