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Archive for June, 2016

Fix X-pessimism in Netlists with Practical Techniques

Thursday, June 30th, 2016

Most functional verification is done before the RTL is handed off for digital synthesis. Gate-level simulations take longer and are hard to debug, but still needed to verify some circuit behavior. Ideally, the output of the RTL simulation will match the output of gate-level netlist simulation after synthesis. But that is not typically the case. Besides the obvious things verified in your gate-level simulations, there are always unknown values (Xs). Some will not be seen in the RTL due to X-optimism, but there will be additional Xs in the gate-level simulations due to X-pessimism.

X-optimism in RTL and other generic issues around unknown states are discussed in more detail in the paper ‘X-Propagation Woes – A Condensed Primer‘. Some basic familiarity with the concept is assumed here.

This paper focuses on X-pessimism at the netlist level. It discusses some current techniques and their limitations, and then describes a more efficient X-pessimism strategy based on Real Intent’s Ascent XV. (more…)

In Memory of Dr. Miles Copeland: Innovator and Mentor

Thursday, June 30th, 2016

miles-copelandI had just learned this week that my mentor into the world of EDA, Dr. Miles Copeland had passed away recently.

At Carleton University in Ottawa, Canada, Copeland was the former chair of the Department of Electronics and Professor Emeritus in the Faculty of Engineering and Design. He was an IEEE Fellow and was known for his passion for teaching and research innovation.

In addition to educating two and a half generations of electrical engineers, Copeland had established Carleton’s research capacity in the area of analog and radio frequency integrated circuit design, including the development of computing techniques to enable and reinforce research and learning.

The focus on computing techniques was how I came to work with Copeland. (more…)

How SoC Design is Driving Constraints Management and Verification

Thursday, June 16th, 2016

There were a number of announcements at DAC 2016 in Austin concerning SDC timing constraints verification and management.  Real Intent announced the newest release of Meridian Constraints for sign-off of SoC designs. It features new and unique functional analysis, data-driven debug, and support for distributed design development.

In this blog, I want to cover the drivers for a new kind of Constraints verification tool.

Constraints Management today is clearly different from the pre-SOC and pre-IP eras. The design process is now truly distributed with much legacy and third-party IP in any new SOC design. This implies that the SDC creation process must go through the three steps of (a) aggregation from the component SDCs to an overall SoC-level SDC, (b) refinement of the SoC-level SDC, and (c) dis-aggregation of the SoC-level SDC into SDCs for the synthesis partitions. The key point here being that the synthesis-partition boundaries need not align with the logical boundaries of the component IPs. (more…)

HOT Party at DAC in 3D

Thursday, June 16th, 2016

hot-party-dac-2016The night of Monday June 6 in Austin was the awesome Heart of Technology (HOT) party and fundraiser for CASA of Travis County that was hosted by Jim Hogan and lots of sponsoring companies that were at DAC.

At the front of the Speakeasy was Killer Tofu, Boston’s premier 90’s band, rockin’ the tunes and getting everyone dancing.

At the back of the venue was Sri Saripalle of Random Designs CA Inc. and his 3-D scanner.   He was doing whole body scans so you could get a 4 inch-high figure as a memento of the event.  Of course, getting the 3D print of myself isn’t free, but I think the charge is quite reasonable.

Here he is the preview of the scan.   The password in GB_DAC16  Click and drag to change the orientation. Do you think it looks like me?  I will update this blog when I get my hard-copy. (more…)

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