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Archive for May, 2016

DAC Preview: 6 Tech. Presentations, Panel on Verification Cost, and the BEST Parties!

Thursday, May 26th, 2016

Real Intent is bringing its advanced Ascent and Meridian technology, EDA expertise and espresso energy to the 53rd Design Automation Conference (DAC) in Austin, Texas, June 5-9, 2016. Before I mention the BEST DAC parties, Real Intent invites attendees to Booth #527 to:

  • Learn the latest information about Real Intent’s Ascent family of tools for the fastest static RTL verification prior to synthesis and simulation, and its Meridian tools that enable CDC and SDC sign-off at the RTL and gate-level.
  • View technical presentations to get up to speed on Real Intent’s latest advancements, proven on giga-gate SoC and FPGA designs. Click here to make an appointment for one of our private suite presentations:
    • How to Accelerate Your RTL Sign-off
    • Ascent Lint with New Visualization and VHDL 2008
    • Meridian CDC with New Analysis and Data-driven Flow
    • Ascent XV with Advanced Gate-level Pessimism Analysis
    • Case Studies in Physical CDC Analysis for Gate-Level Sign-off
    • New Next-Generation Constraints Exception Verification
  • Complete a quick verification survey to be entered into drawings for a cool Roku 4 streaming player and an Amazon Echo wireless speaker and voice commander.
  • Espresso Yourself and enjoy a high-speed coffee from our DeLonghi Magnifica super-automatic coffee machine, to celebrate faster verification and design.
  • Visit Real Intent and OpenText (Booth #638), Real Intent’s “Espresso Yourself” partner at DAC; get a ticket stamped by both companies to enter drawings to win $100 Amazon Gift Cards.
  • Receive a rose as a sweet thank-you gift.


The Switch from Atrenta to Real Intent for CDC, Lint, and X-prop

Thursday, May 12th, 2016

John Cooley’s web-site likes to publish end-user experience with various EDA tools.  On May 6, he published a posting on why a designer switched from Atrenta SpyGlass to Real Intent for CDC, Lint, and X-propagation analysis.  His report details the reasons for converting to our best-in-class tool suite.

Here is the first part of the posting:

We had been using SpyGlass from Atrenta, and it worked OK for us, but we
were told by our local Real Intent sales guy that “there would be fewer
iterations for Lint, easier setup for CDC, lower-noise reporting, and
faster runtimes” — if only we evaled his tools.


I spent one work week (5 days) evaluating Meridian CDC. We used different
designs to evaluate this tool. The first was 850K gate design that had
3 asynchronous clock domains. For the analysis setup, Meridian CDC
automatically detected all the clock/reset candidates correctly at block-
level as well as the top-level. No additions were needed for the setup
file, while our Spyglass run did require manual editing of the setup.
The Meridian runtime for this block was ~5 minutes.

The second design was 4 million gates and had 5 asynchronous clock domains.
Again the automatic clock/reset detection worked as expected. The runtime
was ~15 minutes.

Read the rest of the report on CDC, lint and X-propagation here.

Have you switched EDA tools recently?  How was that experience?

May 17 Event: More than Moore – Enabling the Power of System Scaling

Thursday, May 12th, 2016

More than Moore – Enabling the Power of System Scaling:
An Open Discussion About Design and Manufacturing Challenges

Join the ESD Alliance on the evening of May 17th at 6PM when we will be hosting an open dialogue about system scaling solutions and what it will take to propel them into the mainstream for semiconductor design and manufacturing. Although various system scaling technologies (such as interposer-based designs, using die-level IP blocks, like HBM) are already in use today, they have not yet crossed into the mainstream.

MultiChip Module

System scaling offers an excellent alternative path to pursuing Moore’s Law by moving the integration focus from the transistor to the integration of several heterogeneous pre-fabricated and proven devices, in the form of die-level IP, into an advanced IC package. Although new sub- 10nm process technologies continue to drive Moore’s Law, development cost and times at these advanced nodes are beyond the reach of much of the mainstream market.

It will take collaboration and cooperation between modeling, design, analysis/verification, manufacturing and test in order to unlock the potential of these new integration solutions. The objective for the meeting is to have an open discussion to identify the highest priority issues that should be jointly worked on to streamline the path to widespread adoption. The ESD Alliance is in the process of forming a working group representing both manufacturing and design to work on practical solutions and is seeking community input on direction and priorities.

This is an open event and we encourage anyone who is involved with or interested in system scaling from either the design or manufacturing perspective to attend. Please join us at 6 pm for networking, food and beverages prior to the open discussion forum, starting at 6:30.

Register Now!
Register Now!
There is no charge for this event.
Bob Smith, Executive Director, ESD Alliance
Herb Reiter
, President, eda2asic Consulting, Inc.
Event Details:
Date: Tuesday, May 17 th , 2016
Time: 6:00 PM – 8:00 PM
6:00 PM – 6:30 PM – Registration and networking
6:30 PM – 7:30 PM – Presentations
7:30 PM – 8:00 PM – Discussion
Location: ESD Alliance (SEMI)
3081 Zanker Rd.
San Jose, CA 95134
S2C: FPGA Base prototyping- Download white paper

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