Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
How Physical Implementation Can Break Your Clock-Domain Crossing Logic
March 31st, 2016 by Graham Bell
At DVCon’16, Mark Litterick presented a paper and presentation on “Full Flow Clock Domain Crossing – From Source to Si.” Here is the abstract for the paper:
Functional verification of clock domain crossing (CDC) signals is normally concluded on a register-transfer level (RTL) representation of the design. However, physical design implementation during the back-end pre-silicon stages of the flow, which turns the RTL into an optimized gate-level representation, can interfere with synchronizer operation or compromise the effectiveness of the synchronizers by eroding the mean time between failures (MTBF). This paper aims to enhance cross-discipline awareness by providing a comprehensive explanation of the problems that can arise in the physical implementation stages including a detailed analysis of timing intent for common synchronizer circuits.
Mark works for Verilab as senior verification consultant and holds the position of fellow. He is based in Munich, Germany. To see more of Mark’s technical papers, check out his profile page on the Verilab web-site.
Even though, you may have signed-off for CDC at RTL, logic synthesis, design-for-test and low-power optimization tools can break CDC at the gate-level, the physical implementation stage of design. Real Intent’s Meridian products provide clock-domain crossing verification and sign-off. Our most recent offering is Meridian Physical CDC and provides sign-off at the netlist level of the design. It uses a mix of structural and formal methods to identify glitching and other errors that break the correct registration of signals crossing clock domains.
In his conclusion, Mark states:
The main advantage of running CDC analysis on the final netlist (as well as the RTL sign-off stage) is to pick up additional structural artifacts that were introduced during the back-end synthesis stages such as additional logic on CDC signal paths that might result in glitches, and badly constrained clock-tree synthesis which could for example destroy an intended derived clock structure. The tools use the same fundamental clock domain and synchronizer protocol descriptions as the RTL phase and can therefore assess if some high-level intent has been compromised.
His last word is:
Finally, we would recommend a methodology which involves an explicit dedicated CDC and synchronizer review as part of the final pre-silicon sign-off criteria prior to tape-out.
Physical implementation of RTL designs can break the logic for CDC of signals. A gate-level sign-off for CDC is necessary for modern SoCs or chip failures will be occur in production parts.