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Graham Bell
Graham Bell
Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »

DVCon Recap

March 3rd, 2016 by Graham Bell

The Design and Verification Conference in Silicon Valley delivered the goods again this year. Here are some quick highlights from the show.


Graham talking to Koko and Pippa at the Oski Tech booth.

Wally Rhines, Chairman and CEO of Mentor Graphics gave another engaging, informative and amusing keynote presentation.  Wally took us down through the years with his talk titled “Design Verification Challenges: Past, Present and Future.”  Here is the summary slide of Wally’s presentation that captures the major ideas of his talk.


On Tuesday evening, Jim Hogan spoke with Ajoy Bose, former CEO of Atrenta, on his career building multiple businesses in the technology industry.  He started with AT&T and then later on founded Interra which led to the inception of Atrenta and the SpyGlass product.  He mentioned the importance of two mentors in this success. I know only some small pieces of Ajoy’s story and found his history to be in many ways the history of Silicon Valley.  Ajoy’s one-on-one with Jim was video recorded, and will be available in the near future on the EDA Consortium web-site.

On Wednesday were two conference panel and a sponsored lunch panel by Cadence.  The first panel on “Redefining ESL” certainly exposed the reality that ESL (Electronic Systems Level) is not just 4 0r 5 technology components but more like 15 or more.  This makes the transition from Gate-level to RTL design which involved just a small set of technologies much less daunting that the transition from RTL to ESL design.  Panelists from the EDA companies said we are getting there is incremental steps.  Those in the audience at the microphone pushed for an even wider definition of ESL.  This panel was also video recorded and will be available at a future date.

The sponsored lunch panel was on the topic “Software Driven Verification with Portable Stimulus: The Next Productivity Leap Enabling the Continuum of Verification Engines.”  Frank Schirrmeister of Cadence Design Systems was host and presented how the new portable stimulus standard will be useful in keeping different verification working with maximum efficiency by using a high-level stimulus definition.  The panel was also video recorded and will be available at a future date.

In the afternoon on Wednesday was the panel sponsored by Real Intent and hosted by Jim Hogan: “Emulation + Static Verification Will Replace Simulation.”  At the beginning it seemed all the panelists were in agreement that we were not going to replace simulation. Panelist Brian Hunter from Cavium was particulary adamant that this was the case and necessary for clearing maximum bugs at lowest cost.  Lauro Rizzatti, a verteran emulation executive, made his pitch that we should be using more emulation and that it is the most cost effective way to get to design sign-off.  Pranav Ashar make the point only static verification can handle some of the problems facing design teams, and used the example of CDC verification.  This panel was also video recorded and will be available at a future date.

The next DVCon events are in India and Europe in September and October respectively.  I am sure they will be engaging and informative as our Silicon Valley event was this week.

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