Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
Free Panels and Keynote at DVCon in Silicon Valley
February 25th, 2016 by Graham Bell
You will glad to know that the free Exhibits-Only registration for the Design and Verification Conference (DVCon) that is taking place Feb. 29 through Mar. 3, gives you access to the Tuesday keynote by Wally Rhines of Mentor, and the two panels on Wednesday. And don’t miss the Tuesday evening reception hosted by EDAC, which finishes with Jim Hogan speaking with Dr. Ajoy Bose (Atrenta) about his experiences building multiple successful companies. Your DVCon registration gives you free access to this event.
Here are more details on the panels, one of which is organized by Real Intent.
Emulation + Static Verification Will Replace Simulation — Wednesday March 02, 1:30pm – 2:30pm | Oak/Fir
Moderator: Jim Hogan – Vista Ventures
Emulation and static verification have both been on a tear lately. With processor frequency at a plateau of few GHz and the “processor + system architecture + software” combine still catching up to the parallelism imperative, emulation has stepped up to fill the void nicely. Almost all chips go through some combination of emulation or FPGA-prototyping prior to product release. With a cloud-based pay-as-you-go model, emulation doesn’t even have to be expensive. Emulation is all about speed – the only way to push through stimuli through a high-end SOC.
Likewise static verification is also on a steep upward spiral with almost universal adoption of targeted tools for sign-off verification problems like CDC as well as increasing adoption for problems like power management, reset analysis, X-verification, timing exceptions, security, SOC integration etc. System-level functional formal verification has been on a slower but also positive adoption trajectory. On verification problems where they work well, static methods have come to deliver enhanced productivity and sign-off level confidence. Static tools ensure that design quality is already extremely high before simulation or emulation is started.
May be the verification paradigm of the future is to invest in high-end targeted static verification tools to get the design to a very high quality level, followed by very high-speed emulation or FPGA-prototyping for system-level functional verification. Where does that leave RTL simulation? Between a rock and a hard place! Gate-level simulation is already marginalized to doing basic sanity checks. May be RTL simulation will follow. Or will it?
Redefining ESL — Wednesday March 02, 8:30am – 9:30am | Oak/Fir
Moderator: Brian Bailey – Semiconductor Engineering
Organizers: Dave Kelf – OneSpin Solutions GmbH, Nanette Collins – Nanette V. Collins Marketing and Public Relations
Brian Bailey of Semiconductor Engineering recently wrote an article titled, “What ESL Is Really About.” ESL is not a design flow, he noted, it is a verification flow, and it will not take off until the industry recognizes that. With as many views as there are fragmented pieces of ESL, panelists will have plenty of angles to consider as they discuss raising the abstraction from the register transfer level (RTL) for both design and verification. For example, HLS raises design abstraction, but only works well for certain parts of the design. Portable stimulus raises the abstraction of test specification. Formal works at this level because assertions can be written similarly to parts of the specification. It is a fragmented mess –– different inputs to the main design effort the starts at RTL –– that will be a lively debate.DVCon attendees are invited to join Brian and a panel of distinguished experts who will attempt to define ESL verification, from tools to flows. They will attempt to answer: How or when can all the disparate pieces be brought together, or is that even necessary?
Adnan Hamid – Breker Verification Systems, Inc.
Dave Pursley – Cadence Design Systems, Inc.
Bryan Bowyer – Mentor Graphics Corp.
Simon Davidmann – Imperas Software Ltd.
Raik Brinkmann – OneSpin Solutions GmbH
Patrick Sheridan – Synopsys, Inc.