Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
Super Bowl 50, and Semiconductor and Design Predictions for 2016
February 4th, 2016 by Graham Bell
Super Bowl 50 is being played this Sunday, Feb. 7 to determine the champion of the National Football League (NFL) for the 2015 season. It will be held at Levi’s Stadium in Santa Clara, California, between the National Football Conference (NFC) champion Carolina Panthers and the American Football Conference (AFC) champion Denver Broncos. The game will be played about 6 miles from my house in the East Bay, but I will be enjoying the event on television. There will be the usual collection of interesting commercials and the half-time entertainment will include the band Coldplay and feature Beyoncé and Bruno Mars. My prediction is that the Panthers will beat the spread and defeat the Broncos by more than 6 points. I have not made any cash bets. Yet.
Brian Bailey at SemiEngineering.com does an annual survey of companies in the semiconductor ecosystem for their predictions of what will happen in 2016. His articles (Design; Semiconductor, Manufacturing and Design; Tools and Flows) published several of my comments. I did want to share with you the rest of my predictions and they are all given below. Enjoy!
The Global Semiconductor Industry Survey from KPMG LLP that was published in December, 2015 identifies a number of important trends for the year 2016 based on the response of Semi industry CEOs. I have highlighted the ones I think are most important for the EDA and Design communities and put my comments in parenthesis ():
With the expected consolidation, there will be fewer companies purchasing EDA tools. This will benefit the Big Three companies, and will put additional pressure on Tier 2 and startup companies to differentiate their offerings and maintain product pricing.
The NAND process roadmap from TechInsight below gives us a preview to what will happen in 2016 for technology development. Samsung and Toshiba/SanDisk will introduce their 12(10) nm technology node to the memory marketplace. Micron/Intel and SK Hynix will be playing catch-up to reach Samsung and Toshiba/SanDisk in the 3D memory space. The introduction of their 32-level offerings will provide 192Gb parts in the marketplace.
We have talked about consolidation in the semiconductor industry and we should consider what will be the trend for EDA companies. The Big Three will continue to expand their portfolios for companies which are a part of the electronic system design ecosystem, but not focus on traditional EDA companies. Automotive, embedded software, software design, and also design IP will be target areas that will receive attention in 2016, so we should see acquisitions from there.
Verification companies like OneSpin and Real Intent will become more visible in 2016 as alternatives to the Big Three. Their turn-on-a-dime support will distinguish them from the “take a ticket and wait” model of the larger companies. In addition, they will expand the kinds of failures they can quickly identify.
What about the broad adoption of formal technologies in verification? The Wilson Research and Mentor Graphics 2014 Functional Verification Study gives us a strong trend as shown in the following graphic.
The adoption of static verification for design projects has jumped 62% in two years from 2012 to 2014. This growth rate makes it one of the fastest growing segments in functional verification. I predict this trend will continue and in 2016 automatic formal will exceed the adoption of formal property checking (where designers write their own properties).
What is in this automatic formal category? Harry Foster of Mentor Graphics identifies a list of these applications including SoC integration connectivity checking, deadlock detection, X semantic safety checks and coverage reachability analysis. I would add clock-domain crossing, reset-domain crossing, X-optimism and X-pessimism analysis, timing constraint validation, and lint checks to the list as well.
The continuing growth in the size of SoCs, and in adoption of heterogeneous IPs is clearly driving this trend. To complete functional verification of these large designs, teams are turning to emulation and FPGA prototyping. We can see the adoption by design size in the following graphic. It is expected that FPGA prototyping will grow in 2016 for those designs over 80M gates as easier to use solutions are introduced to the marketplace.
A panel discussion of how Emulation + Static Verification Will Replace Simulation is happening at DVCon 2016 in Silicon Valley. It will discuss in depth these important trends in functional verification and be hosted by Jim Hogan. Expect a lively discussion.
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