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Dr. Roger B. Hughes, Director of Strategic Accounts
Dr. Roger B. Hughes, Director of Strategic Accounts
Dr. Roger B. Hughes is a renowned international expert in formal verification technologies and has over 20 years experience in the EDA industry working both at start-up companies in lead engineering roles and publicly traded companies in managing and directing technical product development. He … More »

CDC Verification of Fast-to-Slow Clocks – Part 3: Metastability Aware Simulation

January 28th, 2016 by Dr. Roger B. Hughes, Director of Strategic Accounts

We continue the short blog series that addresses the issue of doing clock domain crossing analysis where the clocks differ in frequency. In Part 1 and Part 2, we discussed the use of structural and formal checks when there is a fast-to-slow transition in a clock domain crossing. In this blog, we will present the third and final step using a design’s testbench.

The next step in the verification process of fast-to-slow clock domain crossings is to do metastability-aware simulation on the whole design. When running a regular simulation test bench, there is no concept of what could happen to the design if there was metastability present in the data or control paths within the design. One of the key reasons for doing CDC checks is to ensure that metastability does not affect a design. After structural analysis ensures that all crossings do contain synchronizers, and formal analysis ensures that the pulse width and data are stable, a whole-chip metastability-aware simulation is needed to see if the design is still sensitive to metastability. Functional monitors and metastability checkers are shown in Figure 7. No changes are made to the design, and the necessary monitors and checkers are written in an auxiliary Verilog simulation test bench file. This auxiliary file is simply referred to by the original simulation test bench file to invoke the metastability checking. As a prerequisite, this step requires that the design have a detailed simulation test bench.

Figure 7 – Metastability aware simulation checks the tolerance of downstream logic to the presence of jitter in the data path through the use of functional monitors and CDC checkers.

Meridian CDC enables metastability simulation sign-off by offering two capabilities. First, it randomly inserts cycle jitter onto the control or data crossings to mimic the metastability effect; Second, it writes simulation checkers to catch violations during simulation. This combined effect enables metastability simulation sign-off using Meridian CDC.


To provide rigorous clock domain crossing checks on a design, especially one containing transitions of a fast-to-slow nature, three steps must be done.

  1. Use structural checking to ensure all crossings – including fast-to-slow clock and slow-to-fast clock – are CDC safe. This means that all crossings have been checked to have the data switched via a control signal that has the appropriate levels of synchronization.
  2. Use formal verification on all CDC crossings to ensure control signals have a sufficient pulse width to enable the receiving domain clock to capture the transmit domain’s control pulse. This step is especially important for all fast-to-slow clock domain crossings. Use formal analysis to examine the data transitions for data stability. These checks are PULSE_WIDTH and DATA_STABILITY, respectively.
  3. Use metastability-aware simulation on the entire design with an existing simulation test bench to insert random metastability into data and control crossings. Run the simulation against specialized checkers that are automatically generated to prove that the design is not sensitive to metastability.

After these three steps are carried out, designers will have full confidence that the fast-to-slow clock domain crossings are analyzed correctly.


Modern CDC tools, such as Meridian from Real Intent, provide a mix of approaches for sign-off of clock domain crossing analysis. Three techniques were progressively discussed when fast-to-slow clocks were used. Structural checks can be quickly run even on large designs on the whole design When a design is has passed structural analysis, formal checks of certain crossings can be done locally. This is required for all fast-to-slow clock transitions of control signals, either on the feed-forward circuit or on the feedback circuit, depending on which circuit has a fast-to-slow transition. Finally, simulation test benches can be augmented with random metastability injection and checkers to verify that the design is tolerant of metastability.

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