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Archive for December, 2015

DeepChip.com Survey: “Real Intent to possibly replace SpyGlass?”

Thursday, December 17th, 2015

 


It’s not a BUG, it’s a FEATURE!

John Cooley at DeepChip.com does an annual survey of visitors to the Design Automation Conference to find out what was interesting, and the biggest lie.

In one of his roll-up articles he looked at Real Intent, Atrenta (acquired by Synopsys), and One Spin.

With acquisitions, customers get nervous and for good reason.  The support and responsiveness they get changes.  Five respondents said they were considering possibly replacing SpyGlass with Real Intent.  One user reported the following conversation:

“Your SpyGlass customer support won’t change as a result of the SNPS acquisition.” They actually said that to me with a straight face.

The article also reported a customer evaluation of our Ascent Lint and Meridian CDC (clock-domain crossing) tools. Here is a quick snippet: (more…)

Best of “Real Talk”, Q4 Summary and Latest Videos

Thursday, December 10th, 2015

Real Intent has had an exciting 2015!  In the last few months we had a new release of Meridian CDC, a new distribution partner in Israel, and seen many of you at trade shows in China, Israel, Japan, and Germany.  Our YouTube video channel keeps you up to date on all the latest developments at Real Intent, with our most recent on Why A New Gate-level Physical CDC Verification Solution is Needed and X-pessimism: Why do We Care, and What are the Wrong and Right Fixes for it?.  I also discussed “New Physical CDC Sign-off and iDebug analysis” with Sanjay Gangal in an ARM TechCon video interview.

There have been over 50 postings on the Real Talk blog this year, and I have selected the most popular ones read by the EDACafe audience. Here are the top seven:

Is SystemVerilog the COBOL of Electronic Design?
Good news! The Next Big Thing in Verification is Already Here
A Personal History of Transaction Interfaces to Hardware Emulation
In fond Memory of Gary Smith
The Many Tentacled Monster Under My House (with pictures)
Taking Control of Constraints Verification
Billion Dollar Unicorns

Look for more postings on requirements for RTL sign-off in the coming year.

Happy Holidays!

Exposing and Eliminating X-optimism Bugs in RTL

Thursday, December 3rd, 2015

X-optimism occurs when an unknown X value is incorrectly resolved to a known value in RTL simulation. Optimism issues can be difficult to detect and debug because the X is no longer visible once the optimism occurs. The functional issue may not show up at an output for many, many clock cycles after the optimism. X-optimism issues also show up in a gate-level netlist or FPGA-based prototypes, but debug is difficult due to limited visibility in FPGAs, and netlist designs are less familiar post-synthesis. Trying to find an X-optimism bug in an FPGA model is like looking for a needle in a haystack due to limited visibility. In netlist simulations the design hierarchy is flattened, signal names changed, and there is a danger that the X under consideration will be mistaken for a pessimistic node and forced to a known value that hides a functional issue.

Real Intent’s Ascent XV uses static analysis to identify potential X-optimism issues at RTL so they can be fixed prior to simulation, ensuring efficient and accurate simulations. Fixing optimism issues in RTL streamlines getting netlist simulations or FPGA-based prototypes, up and running faster and reduces costly iterations. (more…)

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