Prakash Narain, President and CEO, Real Intent
Prakash's career spans IBM, AMD and Sun where he got hands on experience with all aspects of IC design, CAD tools design and methodology. He was the project leader for test and verification for UltraSPARC IIi at Sun Microsystems. He was an architect of the Mercury Design System at AMD. He has … More »
Is Silicon the New Fabric for Our Lives?
October 22nd, 2015 by Prakash Narain, President and CEO, Real Intent
The following CEO Insight was published in the October 2015 issue of SiliconIndia.
This year we are celebrating the 50th anniversary of Moore’s Law. On April 19, 1965, Electronics magazine published an article that profoundly impacted the world. It was authored by a Fairchild Semiconductor R&D Director, Gordon Moore, who forecast that transistors would decrease in cost and increase in performance at an exponential rate. The article predicted the availability of personal computers and mobile communications. Moore’s seminal observation became known as ‘Moore’s Law’, a prediction that established the path the semiconductor industry would take for the next 50 years or more and, in doing so would dramatically change our lives. Three years later Gordon Moore co-founded Intel, the number one semiconductor company in the world.
According to the analytics firm IHS, the pace of Moore’s Law has resulted in $3 trillion dollars in added value to the Global Domestic Product (GDP) in the last 20 years. We have seen advances across a wide range of business sectors including transportation, energy, life sciences, environment, communications, entertainment, finance, and manufacturing.
In the communications sector there are 6.8 billion mobile phone subscriptions worldwide, or about one per person. More than half of these, 3.6 billion, are so-called smartphones that enable a social media community of 2 billion users.
The power of Moore’s Law has enabled the creation of semiconductor Systems-on-Chip (SoC) that provide rich feature set, brilliant graphics and wireless connectivity that we have learned to take for granted in our smartphones. We tend to overlook the fact that today’s SoCs include hundreds of millions of digital logic gates.
The creators of these SoCs must use computer automation and off-the-shelf design components to assemble working designs in a reasonable amount of time. The complexity of today’s digital chips exceed people’s capability to design and verify them manually.
We, of course, expect our consumer electronics products to work reliably and exhibit long battery life. For automotive, medical, aeronautical, and military applications, requirements for reliable operation are far more strict. Careful automated analysis is needed to confirm correct behavior of designs.
And what is the cost of failure? Currently, the design and fabrication cost for a new SoC ranges from $35-50 million dollars.
Given the huge complexity and feature requirements for SoCs, design verification must start as early in the design process as possible. The digital design community checks basic functionality at the architectural level and begins to implement behavioral designs through the use of hardware description languages such as SystemVerilog and VHDL. The Hardware Description Language (HDL) stage describes how signals will move between the composite digital components; at this stage designers can begin to code different tests that will confirm correct interoperation of the blocks.
With the relentless march of Moore’s Law, we see that the number of engineers required to verify the behavior of a design exceeds the number of engineers needed to develop the design itself. According to Wally Rhines, Chairman and CEO of Mentor Graphics Corp., if this trend continues, the entire population of India will need to become verification engineers.¹
How Can We Contain this Verification Explosion?
By constraining the verification challenge to a series of specific problem areas, such as signals crossing block boundaries, only necessary information must be retained and processed for each specific problem. A narrow focus keeps the problem size manageable. The use of static analysis methods fits very well with the narrow focus technique. Analyzing the intent of the design as it relates to that problem brings dramatic speed-ups; validation results are delivered in minutes, not days as happens with traditional simulation methods. Parallelization of the effort across multiple problem domains means verification is not constrained, and a whole suite of applications can be run concurrently.
After the HDL stage, designs go through what is called digital synthesis – one step closer to physical realization with actual logic gates. Other new verification technologies such as hardware emulation further confirm the correct behavior of an SoC before it is fabricated.
Worldwide demand for electronic devices continues to escalate. Recently semiconductor market research firm IC Insights raised its projection for wearable electronics revenues in 2015 to show much stronger growth in wearable systems after the launch of Apple’s first smartwatches in April 2015. The long-term fate of smartwatches continues to be debated. Whether these wearable systems evolve into a major end-use market category or simply become a niche with a short lifecycle remains to be seen. In the short-term, however, the launch of the Apple Watch — jam-packed with ICs, sensors, and other components — has provided a major boost to semiconductor unit shipments and sales in the wearable Internet-of-Things (IoT) category. IC Insights accordingly has estimated that the wearable IoT category will grow from $1 billion in 2014 to more than $5 billion in 2015.
With addition of more interconnected digital electronics to the fabric of our lives, we will need to continue to develop smarter methods to verify that everything is working correctly. The way forward is clear: verify early, be targeted in your analysis, and parallelize your efforts. Moore’s law is continuing to deliver exciting new opportunities to the world of design, manufacturing and services. Let’s all keep enjoying the new vistas opening up to us.
¹ From his DVCon 2013 keynote presentation, Accelerating EDA Innovation through SoC Design Methodology Convergence, February 26, 2013.