Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
On-the-Fly Hardware Accurate Simulation, New Meridian CDC, ASICON Tutorial
October 8th, 2015 by Graham Bell
In this blog, we are presenting the highlights from Real Intent’s Fall 2015 Verification Newsletter. First are some thoughts from Prakash Narain, CEO, followed by an introduction to the new 2015 release of Meridian CDC for clock-domain and reset-domain crossing sign-off, and finally a review of our fall events including an ASICON tutorial.
Thoughts From Prakash Narain, President and CEO…
Most functional verification for SoC and FPGA designs is done prior to RTL hand-off to digital synthesis, since gate-level simulations take longer to complete and are significantly harder to debug. However, gate-level simulations are still needed to verify some circuit behavior. Unfortunately, X’s in gate-level simulations can cause differences in the RTL simulation output and the gate-level simulation output. X’s generally exist in all designs – it can be difficult to prevent this for practical reasons. Simulation results may be different because of X’s that are hidden in the RTL simulation by X-optimism, or additional X’s may exist due to X-pessimism in gate-level simulations. Pessimism can be fixed by overriding the simulator because you know that real hardware would always resolve to a deterministic value. The challenge is confirming that the X value is a result of X-pessimism and not simply X-propagation, and then forcing it to the right value at the right point in time so the simulation matches that of real hardware.
New Meridian CDC Release with Next-Generation Features
In September we delivered the latest 2015 release of Meridian CDC for comprehensive clock-domain crossing (CDC) and reset-domain crossing (RDC) analysis. This new software release adds enhanced speed, analysis and debug support, boosting productivity for SoC and FPGA design teams. With a brand new way to debug CDC violations, it lets you achieve giga-gate capacity verification without sacrificing precision. We believe it is the industry’s fastest-performance, highest-capacity and most precise CDC solution in the market.
Some of the features of the latest Meridian CDC include:
For additional insights and comments, please watch a video interview here.
Come Visit Us at Upcoming Industry Events
During October and November we will exhibit our Ascent and Meridian solutions at major industry events in Japan, China, Europe and Israel. We were most recently at Design Solution Forum in Yokohama, Japan, on Friday, Oct. 2. Please join us at the International Conference on ASIC (ASICON 2015) Nov. 3-6 in Chengdu, China, where Ramesh Dewangan, our VP of Product Strategy, will present a 90-minute tutorial “New Challenges and Techniques for Clock Domain Crossing and Reset Sign-off.” You can also see our advanced sign-off solutions at the DVCon EU technical conference in Munich on Nov. 11-12, in area F4, and at SemIsrael in Airport City on Nov. 17. At SemIsrael, Oren Katzir, our VP of Applications Engineering will present a talk “New RTL sign-off challenges: Reset metastability, X-safe design, and CDC Data glitches.”