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Lisa Piper, Senior Technical Marketing Manager at Real Intent
Lisa Piper, Senior Technical Marketing Manager at Real Intent
Lisa Piper is currently a Senior Technical Marketing Manager at Real Intent. She has extensive experience in simulation-based verification, acceleration and formal verification. Prior to Real Intent, Lisa worked at Lucent Microelectronics and AT&T Bell Labs. She has a BSEE from Purdue … More »

Correcting Pessimism without Optimism – Part Two

October 1st, 2015 by Lisa Piper, Senior Technical Marketing Manager at Real Intent

Part one of this article focused on the issues of X-pessimism at the netlist level and why the current solutions are inadequate.  In In part two, we look at how the Ascent XV tool correctly addresses X-safe verification.

If a node is determined to be 1(or 0) pessimistic, that means its real circuit value is 1(or 0), but simulation produces an X. A pessimistic simulation value can be corrected by forcing a 1(or 0) on the node until the conditions for pessimism no longer hold, at which time, it is released. This does not mean that all X’s can be arbitrarily forced to a known value. Only X’s that result from pessimism should be forced, and they must be forced to represent the deterministic value that real hardware would see and released immediately when the pessimism stops.

Ascent XV-netlist makes your simulation hardware accurate by appropriately correcting pessimism. Ascent XV statically identifies the potentially pessimistic nodes and then uses that information to create SimPortal files that augment gate-level simulation to correct X-pessimism on the fly. By doing the analysis statically before the simulation starts, the number of nodes that must be analyzed during simulation is significantly reduced. Also, the X-analysis during simulation can be reduced to a table look-up when the potentially pessimistic node has an X-value. The SimPortal files monitor the potentially pessimistic nodes in the design on the fly, independent of the testbench.

A bottoms-up hierarchical static analysis can also be done at the block level. When all the blocks are integrated for full chip simulations, a very scalable solution is achieved. The SimPortal is designed for performance, and also minimizes compile time and memory overhead. You can control the verbosity at simulation time, and can choose to drop back to simple monitoring or even turn off both the correction and monitoring at any point in time. The flow and methodology is shown below in Figure 3.


Figure 3. Ascent XV X-Pessimism Flow and Methodology

Ascent XV X-pessimism Flow and Methodology:

  1. Run static analysis to determine which data input values can cause monitored nodes to exhibit pessimism. Generate design-specific SimPortal data files.
  2. Run SimPortal simulation to find out which nodes experienced the input combinations that cause pessimism.

The Ascent XV solution is characterized as follows:

  • Performance
    • Gate-level simulation overhead is as low as 2x-2.5x
    • Memory overhead is 0.5x
    • Negligible overhead to compilation time
    • Simulation time configuration of verbosity from totally quiet to full details
    • Can choose to turn off correction at any point in time (such as after reset)
  • Capacity
    • Unique approach easily handles next generation full chip netlists (billion gate SOCs)
  • Accuracy
    • Only does forces when pessimism is occurring.
    • The value forced is the value that will be seen in real hardware.
  • Ease of Use
    • No setup required
    • Testbench independent static analysis
    • No need to touch the existing design or testbench, only the simulation script

In RTL, X’s can hide functional bugs due to X-optimism. These bugs will be brought to light in netlist gate simulations. Unfortunately, X’s also cause X-pessimism in netlist simulations, making it difficult to determine whether a functional mismatch is due to X-optimism, X-pessimism, or something else entirely. Ascent XV – Netlist will remove X’s caused by X-pessimism, removing the major source of simulation RTL and netlist simulation differences.

Related Considerations

Reliable correcting of pessimism at the netlist has become very feasible, thanks to Ascent XV. But there is additional analysis that can be done early in the RTL development process to prevent potential X-issues. This will benefit the post-RTL handoff, whether it is gate-level simulations or FPGA modeling of your design, so you are not debugging X-optimism issues in hard to debug environments.

Ascent XV- Reset Optimization minimizes significant X’s in the design that result from incomplete initialization. Ascent XV – Reset Optimization will do a hardware accurate reset analysis that will report where additional resets are needed; as well suggest where resets can be removed. It ensures complete initialization, taking into account the propagation of known values to avoid adding extraneous resets. The goal is to minimize X-issues during the design of the RTL. In the case of simulations, fewer occurrences of pessimism will speed your simulation.

Ascent XV-RTL Optimism analyzes where the X-sources of a design are, as well as where they can cause X-optimism. This ensures hardware accurate simulations at RTL either by eliminating the X-source, or through coding for X-accuracy. Hardware accurate RTL simulations will make the RTL-netlist simulation outputs easier to compare, but more significantly, it will make FPGA-based modeling easier to get up and running.


Once a design is synthesized, the immediate goal is to get gate-level simulations up and running fast.  Unfortunately, X’s in gate-level simulations can cause differences in the RTL simulation output and the gate-level simulation output. X’s generally exist in all designs – it can be difficult to prevent this for practical reasons. Simulation results may be different because of X’s that are hidden in the RTL simulation by X-optimism, or additional X’s may exist due to X-pessimism in gate-level simulations. Pessimism can be fixed by overriding the simulator because you know that real hardware would always resolve to a deterministic value. The challenge is confirming that the X value is a result of X-pessimism and not simply X-propagation, and then forcing it to the right value at the right point in time so the simulation matches that of real hardware.

Ascent XV- Netlist Pessimism corrects X-pessimism on the fly so the simulation is hardware accurate. Use of Ascent XV saves in the time required to get gate-level simulations started by an order of magnitude.  It is proven to be superior to alternative approaches in the marketplace in terms of performance, memory, and accuracy.  Its ease of use and capacity, make it the only practical solution for large SOCs.

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One Response to “Correcting Pessimism without Optimism – Part Two”

  1. Kevin Cameron says:

    As someone pointed out to me in the 90s: the “X” piece is conceptually orthogonal to signal values, so a large part of the problem with “X pessimism” is self-inflected by using a bad signal model in Verilog i.e. the compact 0-1-X-Z. Both VHDL and System Verilog allow user defined types which let you separate the components so you can have consistent 1/0 values in addition to an X component which will tell you if the 1/0 is trustworthy.

    E.g. we lost some time in verification due to someone not wiring power into a level-shifter and the level-shifter just pumping out “X”. With a different model the level shifter would pass through the logic 1/0 and set a flag to say it’s not trusted because the power was off – that lets you do downstream (functional) verification without waiting for power to be wired up.

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