Archive for October, 2015
Thursday, October 29th, 2015
Many years ago, my wife and I bought our first home. At that time, a coworker said to me, “Congratulations! You now have a home project to do every weekend for the rest of your life!” How right he was, though his prediction only covered our first 6 years, since we had sold that early house and moved into an apartment in San Francisco.
Fast forwarding to this past summer, our family made the decision to move back to the south bay. We located a nice house near a good elementary school within our budget, and moved in over the Independence Day weekend. Part of the move involved pulling my old woodworking tools out of storage. (Back when we first moved to the City, I’d tried with no success to convince my wife that a table saw sitting in the middle of our living room in our small apartment really wouldn’t be an inconvenience.) For me, setting up the tools once more was like seeing long absent friends. As they took their new places in our garage, my thoughts turned to how to use them to make “improvements” in our new home.
Thursday, October 22nd, 2015
The following CEO Insight was published in the October 2015 issue of SiliconIndia.
This year we are celebrating the 50th anniversary of Moore’s Law. On April 19, 1965, Electronics magazine published an article that profoundly impacted the world. It was authored by a Fairchild Semiconductor R&D Director, Gordon Moore, who forecast that transistors would decrease in cost and increase in performance at an exponential rate. The article predicted the availability of personal computers and mobile communications. Moore’s seminal observation became known as ‘Moore’s Law’, a prediction that established the path the semiconductor industry would take for the next 50 years or more and, in doing so would dramatically change our lives. Three years later Gordon Moore co-founded Intel, the number one semiconductor company in the world.
Thursday, October 15th, 2015
At the Design Automation Conference in San Francisco, Real Intent did a survey of 201 visitors to our booth. We focused on RTL and gate-level verification issues. Below is a brief introduction and you can see the entire survey on the DeepChip.com web-site.
DAC’15 “When is your next design start?”
0-3 months : ########################################### (52%)
3-6 months : ###################### (26%)
6-12 months: ################## (22%)
These numbers are very similar to what was reported in 2012 on DeepChip. With half of the future design starts occurring in the next 3 months, this leads me to think design activity is remaining strong despite any EDA user consolidation we might have seen with the big mergers of various chip companies, and the slowing of the Chinese economy. However, the latest IC forecast from Gartner has 2015 growth falling from 5.4% at the beginning of 2015 down to 2.2% in July.
Thursday, October 8th, 2015
In this blog, we are presenting the highlights from Real Intent’s Fall 2015 Verification Newsletter. First are some thoughts from Prakash Narain, CEO, followed by an introduction to the new 2015 release of Meridian CDC for clock-domain and reset-domain crossing sign-off, and finally a review of our fall events including an ASICON tutorial.
Thoughts From Prakash Narain, President and CEO…
Most functional verification for SoC and FPGA designs is done prior to RTL hand-off to digital synthesis, since gate-level simulations take longer to complete and are significantly harder to debug. However, gate-level simulations are still needed to verify some circuit behavior. Unfortunately, X’s in gate-level simulations can cause differences in the RTL simulation output and the gate-level simulation output. X’s generally exist in all designs – it can be difficult to prevent this for practical reasons. Simulation results may be different because of X’s that are hidden in the RTL simulation by X-optimism, or additional X’s may exist due to X-pessimism in gate-level simulations. Pessimism can be fixed by overriding the simulator because you know that real hardware would always resolve to a deterministic value. The challenge is confirming that the X value is a result of X-pessimism and not simply X-propagation, and then forcing it to the right value at the right point in time so the simulation matches that of real hardware.
Thursday, October 1st, 2015
Part one of this article focused on the issues of X-pessimism at the netlist level and why the current solutions are inadequate. In In part two, we look at how the Ascent XV tool correctly addresses X-safe verification.
If a node is determined to be 1(or 0) pessimistic, that means its real circuit value is 1(or 0), but simulation produces an X. A pessimistic simulation value can be corrected by forcing a 1(or 0) on the node until the conditions for pessimism no longer hold, at which time, it is released. This does not mean that all X’s can be arbitrarily forced to a known value. Only X’s that result from pessimism should be forced, and they must be forced to represent the deterministic value that real hardware would see and released immediately when the pessimism stops.
Ascent XV-netlist makes your simulation hardware accurate by appropriately correcting pessimism. Ascent XV statically identifies the potentially pessimistic nodes and then uses that information to create SimPortal files that augment gate-level simulation to correct X-pessimism on the fly. By doing the analysis statically before the simulation starts, the number of nodes that must be analyzed during simulation is significantly reduced. Also, the X-analysis during simulation can be reduced to a table look-up when the potentially pessimistic node has an X-value. The SimPortal files monitor the potentially pessimistic nodes in the design on the fly, independent of the testbench. (more…)