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Archive for September, 2015

Correcting Pessimism without Optimism – Part One

Thursday, September 24th, 2015

Most functional verification for SoC and FPGA designs is done prior to RTL hand-off to digital synthesis because gate-level simulations take longer to complete and are significantly harder to debug. However, gate-level simulations are still needed to verify some circuit behavior. Ideally, the output of the RTL simulations will match the output of gate-level netlist simulations on the same design after synthesis. And why wouldn’t they? Besides the obvious things that are being verified in your gate-level simulations, there are also unknown values (X’s) that were not seen in RTL due to X-optimism, and additional X’s in the gate-level simulations due to X-pessimism. Part one of this article focuses on the issues of X-pessimism at the netlist level and why the current solutions are inadequate.
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Calypto Design Systems: A Changed Partner

Thursday, September 17th, 2015

Calypto Design Systems was embraced by Mentor Graphics this week.  Founded in 2002, the company was born out of discussions between founder Devadas Varma and Dado Banatao, partner at Tallwood Venture Capital.  By early 2005, it had raised $22 million in venture capital, and had 42 employees, 18 with PhDs.  It was tackling equivalence checking (SLEC) between ESL and RTL design representations.

In 2011, Mentor bought a 51% interest in the company and sold Calypto its Catapult-C synthesis technology, which seemed like a good match to their SLEC tool.  With Calypto’s growing success, it was natural that Mentor would pull them into their fold.

For several years, Calypto Design Systems and Real Intent have co-operated in support of verification flows for mutual customers.  Both companies shared the same distributor is Korea.

One flow we had jointly announced was our Ascent Lint with their Catapult synthesizer.  Catapult lets designers use industry standard ANSI C++ or SystemC to describe functional intent at the ESL level. From these high-level descriptions, Catapult automatically generates production quality RTL.  Ascent Lint ensures Catapult-generated RTL code is lint clean and error free for a safe and reliable implementation flow from RTL to GDSII layout.
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Thunderbolt 3 and USB Type-C: the 40 Gbps + 100W Answer

Thursday, September 10th, 2015

As the computer, tablet and smartphone industries move toward adoption of the new USB Type-C connector, a new version of Thunderbolt is quickly approaching. With speeds topping 40 gigabits per second, Thunderbolt 3 promises to provide another solution to unify various display, docking, power, storage and network protocols currently available under the USB Type-C standard, with data transmission speeds beyond that of USB Type-C as well as other protocols like DisplayPort and PCI Express.

USB and Thunderbolt have been widely used to connect various peripheral devices providing storage, display, and recently, power capabilities though distinct ports on devices. And until now, these ports have been separate. When work by Intel began on the Thunderbolt 3 interface, the port was going to continue to be unique until standards began to emerge for USB Type-C.

A USB Type-C connector.

USB Type-C connector

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The Power of Dynamic Voltage Frequency Scaling

Thursday, September 3rd, 2015

Battery life in consumer electronics is dependent on the dynamic power behavior of their integrated circuits.  If that dynamic behavior can be adjusted to fit the task at hand, then considerable power savings can be realized.  In CMOS circuits most of the dynamic power is consumed in the parasitic capacitance of their digital gates.

The equation for dynamic or transient power can be written as follows:

pwr-eqn
where

pwr-eqn-2

 

 

 

 

 

 

The combination of supply voltage and frequency has a cubic impact on total power dissipation because dynamic power consumption has a quadratic dependence on voltage and a linear dependence on frequency. An intelligent power savings solution would reduce operating frequency and, at the same time, reduce the supply voltage. Some example commercial implementations of dynamic voltage frequency scaling (DVFS) technology are Intel’s SpeedStep and AMD’s PowerNow.  According to the 2014 Calypto RTL Power Reduction Survey, 24% of designs used DVFS.

Click here to read the rest of this article originally published on EETimes SoC Designlines.

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