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Graham Bell
Graham Bell
Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »

Good news! The Next Big Thing in Verification is Already Here.

August 20th, 2015 by Graham Bell

The Wilson Research Group 2014 functional verification study exposes many interesting trends in the techniques used and troubles seen by both designers and verification engineers.  Harry Foster of Mentor Graphics has been been blogging about the study for some time now.

As I was looking over the report slides, there was an interest trend that stood out for me.

Figure 1. The Mean Time that Design Engineers spend doing design versus doing verification.

The first thing I noted is that time spent on doing verification has dropped back to a level previously seen in 2007.

How can this happen? We know that design sizes have continued to inflate, and that the combination of multi-core architectures and new low-power modes has created additional headaches for verification teams.  There is dramatically more verification that needs to be done to get designs signed-off and ready for implementation.  See Figure 2 for the growth trend for ever-larger designs reaching a billion gates.

Figure 2. The size of design projects is quickly approaching a billion gates.

So if the verification challenge is growing exponentially, why is time spent on verification declining?  One trend is that emulation is playing a bigger role in verification.  According to the Wilson study, one-third of the industry has adopted emulation, and for verifying large designs over 80 million gates, almost 60% of companies use emulation. Another trend is the adoption of static technologies which don’t use simulation but a combination of structural intent analysis with automatic formal engines.  The growth of these static technologies has clearly taken off, as shown in Figure 3.

Figure 3. The adoption of static verification for design projects has jumped 62% in two years.

What is in this category? Harry identifies a list of these applications including SoC integration connectivity checking, deadlock detection, X semantic safety checks and coverage reachability analysis.  I would add clock-domain crossing, X-optimism analysis, and timing constraint validation, and lint checks to the list as well.

Harry’s conclusion is that, the growth rate of 62% for formal solutions make it one of the fastest growing segments in functional verification.  At Real Intent, we see this as an important driver for the adoption of our solutions in the marketplace which rely on static techniques.

To me the answer is clear.  Static analysis is the next big thing in verification.  It is essential for handling billion-gate designs and getting to RTL sign-off.

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One Response to “Good news! The Next Big Thing in Verification is Already Here.”

  1. Stephen Bailey says:


    It is incorrect to conclude from the data that less time is being spent in verification. The data are relative to each other. For example, it could be that the time spent in verification is stable or increasing, but the time spent in design has increased (more).

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