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Vinod Viswanath
Vinod Viswanath
Vinod Viswanath is a Director of R&D at Real Intent, where he works on next generation tools to understand and implement low power and timing constraints. Prior to this, he was a researcher in Intel’s low power group working on formal verification of processors and SOC platforms. Vinod … More »

SoC Power Management: Which Power are We Talking About?

June 18th, 2015 by Vinod Viswanath

I agree with the observation that low-power is a largely unsolved problem. We have seen a tremendous change in the past decade and a half in low-power research, particularly in the context of micro-architecture for small devices and embedded systems. The chief catalyst for this research is the unprecedented growth in the proliferation of handheld mobile devices. In today’s design flows, power management has emerged as the second most important challenge, next only to timing closure, ahead of meeting timing and area goals and taping out on schedule.

Process technology for low-power gains has come a long way. In the early days, a low-power process typically meant a 20% hit in performance. Such performance hits are no longer acceptable, and process technology has improved to offer several standard cell height choices with different threshold voltages for different performance, power and density tradeoffs. Despite all these advances, process technology will not deliver all the gains needed in an optimal low-power device. See the figure below.

Power Trend for SoCs in Portable Electronics (ITRS 2011)

Power Trend for SoCs in Portable Electronics (ITRS 2011)

Beyond process technology, power management and optimization research in the last couple of decades has spanned multiple areas of circuit/design optimizations, RTL and micro-architectural techniques for processors, caches, memories, dynamic voltage/frequency scaling of processors and other components, power management of individual components such as hard drives, external memories, and network interfaces. In addition to these, there have been improvements to system-level power management via system power states and thermal management. Software optimizations like power-aware compilers, O/S optimizations for energy efficiency, and system-level dynamic power management provide further optimal power functionality.

Despite these advances, the demands on low-power functionality continue to rise. The key reason for this is an optimal and holistic power management solution cannot be done in hardware or software alone. There is a strong need for a synergistic bottom line across RTL, System level, OS level, Compiler level, and Application level specification of power intent. The kind of information available at a higher level of abstraction at the OS level or even at the Application level, is just not visible to the RTL. We need all levels of abstraction of the design to be able to communicate their power intent to get the most optimized solution.

Due to the lack of hardware/software cooperation in power management, the platform as a whole cannot anticipate power requirements of the application ahead of time and instead, has to perform power management reactively.  This is where standardization can play a key role, by providing a common language of communication between these levels of abstraction. Standardization will also pave the way for general solutions to statically check conflicting requirements at different levels.

From a market segment perspective, there is no single leader for this. EDA, IP, big design, all have to play their part in contributing towards building a holistic power specification and management system. There could be items that are covered by standards, items that are implemented independently by hardware companies, items that are interpreted/implemented differently by different software stacks, etc. The increased power gains will come from smart aligning of different components and better sharing of power information, both statically and at run-time. So far, software abstractions have typically been conservative and dynamic corrections coarse. Fine-grained dynamic power management along the software stack is where bulk of the new age power gains will come from.

Currently, there are three committees, sponsored by IEEE Standards Association (1801-SLP, P2415, and P2416), working towards standardizing the different components along all these levels of product hierarchy.

This issue of hardware-software synergistic fine-grained dynamic power management is not without its controversies. Several folks (including large EDA and design companies) hold the idea that the hardware holds all the cards, and it is up to the hardware to handle the power requirements. However, as any platform architect on a mobile device will testify, in a tiny form factor handheld device, there are extensive optimizations in the O/S drivers, kernel wake-locks, optimizations in middleware like SKIA and openGL optimizations, media and DRM optimizations to deliver compelling media experiences at low- energy rates, etc. Without these optimizations in various levels of software stack and the application code itself, it is not possible to deliver the optimal landing zone for area and power and performance.

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One Response to “SoC Power Management: Which Power are We Talking About?”

  1. Krishna Pawar says:

    Nice Article..!

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