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 Real Talk

Archive for June, 2015

Reset Expectations with X-Propagation Analysis

Thursday, June 25th, 2015

The propagation of unknown (“X”) states has become a more pressing issue with the move toward billion-gate SoC designs, and especially so with power-managed SoC designs. The SystemVerilog standard defines an X as an “unknown” value used to represent the state in which simulation cannot definitely resolve a signal to a “1,” a “0,” or a “Z.”

Synthesis, on the other hand, defines an X as a “don’t care,” enabling greater flexibility and optimization. Unfortunately, Verilog RTL simulation semantics often mask the propagation of an X value, while gate-level simulations show additional Xs that will not exist in real hardware.

The sheer complexity and common use of power management schemes increase the likelihood of an unknown “X” state in the design translating into a functional bug in the final chip. This possibility has been the subject of two technical presentations at the Design and Verification Conference during the last couple of years: I’m Still in Love With My X! But, Do I Want My X to Be an Optimist, a Pessimist, or Eliminated? and X-Propagation Woes: Masking Bugs at RTL and Unnecessary Debug at the Netlist. Let’s look more closely at this issue and the requirements for a solution.

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Last Call for Kaufman Award Nominations

Tuesday, June 23rd, 2015

The EDA Consortium and the IEEE Council on EDA is seeking qualified nominations for the 2015 Phil Kaufman Award.  The nomination deadline is June 30.

Presented by the EDA Consortium and the IEEE Council on EDA, this prestigious award honors an individual who has had demonstrable impact on the field of electronic design through contributions in Electronic Design Automation.  PressRelease.

Additional information on the nomination process is available here.

Information on previous Phil Kaufman Award recipients is available here.

Download the nomination form here.

SoC Power Management: Which Power are We Talking About?

Thursday, June 18th, 2015

I agree with the observation that low-power is a largely unsolved problem. We have seen a tremendous change in the past decade and a half in low-power research, particularly in the context of micro-architecture for small devices and embedded systems. The chief catalyst for this research is the unprecedented growth in the proliferation of handheld mobile devices. In today’s design flows, power management has emerged as the second most important challenge, next only to timing closure, ahead of meeting timing and area goals and taping out on schedule.

Process technology for low-power gains has come a long way. In the early days, a low-power process typically meant a 20% hit in performance. Such performance hits are no longer acceptable, and process technology has improved to offer several standard cell height choices with different threshold voltages for different performance, power and density tradeoffs. Despite all these advances, process technology will not deliver all the gains needed in an optimal low-power device. See the figure below. (more…)

Quick 2015 DAC Recap and Racing Photo Album

Thursday, June 11th, 2015

This years Design Automation Conference in San Francisco was excellent!   You don’t have to take my word for it.  At the Industry Liaison Committee meeting for DAC exhibitors on Thursday June 11, the various members were in agreement that show traffic was up, and the quality of the customer meetings exceeded expectations.  Why is that?  It is in large part of due to the tremendous efforts of Anne Cerkel senior director for technology marketing at Mentor Graphics, who was the general chair for the 52nd DAC.

One innovation at this year’s show was opening the exhibitor floor at 10 am.  This made it more convenient to see the morning keynotes and also more flexibility in commuting to the show from around the Bay area.  I think you can expect to see this again at the next 53rd DAC show in Austin Texas.

Our two GRID racing car simulators was one reason the show was excellent for Real Intent.  We were able to draw a large crowd to our booth.  Budding race car drivers could challenge their friends and colleagues to a race and enjoy our license-to-speed verification solutions.  A special thank you to Shama Jawaid and the team at OpenText who was our partner for the license-to-speed promotion.

Here are some quick photos from the show for you to enjoy.

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Advanced FPGA Sign-off Includes DO-254 and …Missing DAC?

Thursday, June 4th, 2015

One trend we’re seeing in Asia is the number of FPGA design starts — now counting in the thousands. Getting a functionally correct design is the first goal for designers. It is easy to think that once that is achieved FPGAs can shipped out in finished products. But that’s not a robust model. For example, we have had customers with failures in the field due to a subtle timing change between FPGA part lots. Larger FPGA designs have grown in complexity, resulting in an amalgamation of disparate IP that can lead to clock domain challenges. A robust model for FPGA designs requires advanced signoff tools, a design flow that works easily with Xilinx and Altera tools, and support for high-reliability standards like DO-254. This is where Real Intent’s Meridian and Ascent products excel. For high-performance, our CDC and Lint tools provide the confidence design teams need, with unsurpassed verification and sign-off support. 

Come visit us in Booth #1422 at DAC in San Francisco, June 8-10 to see our latest technical presentations. To choose your technical presentation click here.

Can’t attend DAC?  Check out some of our latest video interviews with Real Intent technologists or email us for a personal presentation to you or your team.

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