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Archive for May, 2015

#2 on GarySmithEDA What to See @ DAC List – Why?

Thursday, May 28th, 2015

The last two weeks before the Design Automation Conference in San Francisco are a busy time.  For us marketeers, it has been called “our Superbowl.”  We want to get the word out that we have something new and important to show visitors to at our exhibit booth.  But there is more going on which I will mention after I talk about our booth activities.

Real Intent is number two on the GarySmithEDA What to See @ DAC list.   I know why we are number two on the list.  But I don’t want to give the secret away. If you know the reason, then please let everyone know in the comments section at the end of the blog.

Here are the quick titles for our technical presentation in our demo suites.

  • Ascent Lint with 3rd Generation iDebug Platform and DO-254
  • Meridian CDC for RTL with New 3rd Generation iDebug Platform
  • Ascent XV with Advanced Gate-level Pessimism Analysis
  • Accelerate Your RTL Sign-off
  • Hierarchical CDC Analysis and Reporting for Giga-gate Designs
  • Next-Generation Meridian Constraints for SDC
  • Autoformal RTL Verification
  • FPGA Sign-off and Verification

Click on this appointment sign-up link to arrange a meeting with us. (more…)

SoC Verification: There is a Stampede!

Thursday, May 14th, 2015

Red River Cattle DriveIn the stories of the Wild West from the 1800s, the image of a cattle drive often is depicted. A small team of cowboys delivers thousands of heads of cattle to market. The cowboys spend many days crossing open land until they reach their destination – one with stock yards to accept their precious herd, and a rail station to deliver it quickly to market. Along the way there are dangers, including losses by predators and mad stampedes by cattle rushing blindly when frightened or disturbed. The primary job of the cowboys is to keep the herd on track and settled as they move to ship-out.

I see immediate parallels between the cowboys of the Wild West and today’s system-on-chip (SoC) design and verification engineers. Cowhands struggle to control and move a big herd. Similarly, today’s design teams grapple with how to keep a project on target and converging to tape-out and success when the gate count of SoCs has become so large it can stretch and even overwhelm their ability to stay on track. How big are these new SoCs? (more…)

Drilling Down on the Internet-of-Things (IoT)

Thursday, May 7th, 2015

Did you know there will be 50 billion connected devices by 2020?

I am not making it up!

This was the future painted by Dr. Martin Scott, SVP and GM, Cryptography Research Division, Rambus, in a scintillating session on the Internet of Things (IoT) at the Silicon Summit 2015 event organized by Global Semiconductor Alliance in April.

What will the future look like when there will be more than six devices for every person on the planet?

I’ll summarize what I learned regarding three IoT topics: the components, the scope and the challenges.

Components of an IoT System

Dr. Scott laid out the high-level components of an IoT system: (more…)

S2C: FPGA Base prototyping- Download white paper

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