Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
Smarter Verification: Shift Mindset to Shift Left [Video]
March 5th, 2015 by Graham Bell
The Design and Verification Conference Silicon Valley was held this week. During Aart de Geus’ keynote, he shared how SoC verification is “shifting left”, so that debug starts earlier and results are delivered more quickly. He identified a number of key technologies that have made this possible:
Real Intent has also been talking about this new suite of technologies that improve the whole process of SoC verification. Pranav Ashar, CTO at Real Intent wrote about these in a blog posted on the EETimes web-site. Titled “Shifting Mindsets: Static Verification Transforms SoC Design at RT Level“, it introduces the idea of objective-driven verification:
We are at the dawn of a new age of digital verification for SoCs. A fundamental change is underway. We are moving away from a tool and technology approach — “I have a hammer, where are some nails?” — and toward a verification-objective mindset for design sign-off, such as “Does my design achieve reset in two cycles?”
Objective-driven verification at the RT level now is being accomplished using static-verification technologies. Static verification comprises deep semantic analysis (DSA) and formal methods. DSA is about understanding the purpose and intent of logic, flip-flops, state machines, etc. in a design, in the context of the verification objective being addressed. When this understanding is at the core of an EDA tool set, a major part of the sign-off process happens before the use or need of formal analysis.
The right mix of these two components — DSA and formal methods — significantly reduces the need for dynamic analysis (simulation). Although dynamic analysis continues to have a role, increasingly it is viewed as a backstop and not the main focus of the verification flow. Any simulation must be absolutely necessary and be tied to a companion static analysis step. Click here to read the entire article.
Pranav also covered this topic in a recent interview with Warren Savage, President and CEO of IP Extreme, on his IP Watch YouTube channel. Pranav shares his background in the high-tech industry before the conversation turns to verification and how it has changed over the years.