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Archive for March, 2015

Taking Control of Constraints Verification

Thursday, March 26th, 2015

This article was originally published on TechDesignForums and is reproduced here by permission.

Constraints are a vital part of IC design, defining, among other things, the timing with which signals move through a chip’s logic and hence how fast the device should perform. Yet despite their key role, the management and verification of constraints’ quality, completeness, consistency and fidelity to the designer’s intent is an evolving art.

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Billion Dollar Unicorns

Thursday, March 19th, 2015

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Courtesy of Fortune Magazine, illustration by Jeremy Enecio.

The business magazine, Fortune, in a Feb. 2015 article proclaimed The Age of Unicorns  — private companies valued at more than $1 billion by investors. Unicorns are the stuff of myth, but billion-dollar tech start-ups seem to be everywhere, backed by a bull market and a new generation of disruptive technology.  According to a recent New York Times article, there are over 50 unicorns in Silicon Valley right now.

Upcoming unicorns formed a popular discussion topic at the Confluence 2015 conference organized by Zinnov, on March 12th in Santa Clara, Calif. The conference theme was “Building the Technology Organizations of Tomorrow”.

Here is a sampling of six unicorns that have emerged as real winners using innovative strategies: (more…)

My Impressions of DVCon USA 2015: Lies; Experts; Art or Science?

Thursday, March 12th, 2015

Last week I attended the Design and Verification Conference in San Jose.  It had been six years since my last visit to the conference.  Before then, I had attended five years in a row, so it was interesting to see what had changed in the industry.  I focused on test bench topics, so this blog records my impressions in that area.

First, my favorite paper was “Lies, Damned Lies, and Coverage” by Mark Litterick of Verilab, which won an Honorable Mention in the Best Paper category.  Mark explained common shortcomings of coverage models implemented as SystemVerilog covergroups.  For example, because a covergroup has its own sampling event, that may or may not be appropriate for the design.  If you sample when a value change does not matter for the design, the covergroup has counted a value as covered when in fact it really isn’t.  In the slides, Mark’s descriptions of common errors were pithy and, like any good observation, obvious only in retrospect.  More interestingly, he proposed correlating coverage events via the UCIS (Unified Coverage Interoperability Standard) to verify that they have the expected relationships.  For example, a particular covergroup bin count might be expected to be the same as the pass count of some cover property (in SystemVerilog Assertions) somewhere else, or perhaps as much as some block count in code coverage.  It struck me that some aspects of this must be verifiable using formal analysis. You can read the entire paper here and see the presentation slides here.

I was also impressed by the use of the C language in verification — not SystemC, but old-fashioned C itself.  Harry Foster of Mentor Graphics shared some results of his Verification Survey, and there were only two languages whose use had increased from year-to-year: SystemVerilog and C.  For example, there was a Cypress paper by David Crutchfield et al where configuration files were processed in C.  Why is this, I wondered?  Perhaps because SystemVerilog makes it easy via the Direct Programming Interface (DPI): you can call SystemVerilog functions from C and vice-versa.  Also, a lot of people know C.  I imagine if there were a Python DPI or Perl DPI, people would use those a lot as well! (more…)

Smarter Verification: Shift Mindset to Shift Left [Video]

Thursday, March 5th, 2015

The Design and Verification Conference Silicon Valley was held this week.  During Aart de Geus’ keynote, he shared how SoC verification is “shifting left”, so that debug starts earlier and results are delivered more quickly.   He identified a number of key technologies that have made this possible:

  • Static verification that uses a mix of specialized code analysis and formal technology which are must faster and more focused than traditional simulation
  • New third generation of analysis engines
  • Advancements in debug

Real Intent has also been talking about this new suite of technologies that improve the whole process of SoC verification.  Pranav Ashar, CTO at Real Intent wrote about these in a blog posted on the EETimes web-site.  Titled “Shifting Mindsets: Static Verification Transforms SoC Design at RT Level“, it introduces the idea of objective-driven verification:

We are at the dawn of a new age of digital verification for SoCs. A fundamental change is underway. We are moving away from a tool and technology approach — “I have a hammer, where are some nails?” — and toward a verification-objective mindset for design sign-off, such as “Does my design achieve reset in two cycles?”

Objective-driven verification at the RT level now is being accomplished using static-verification technologies. Static verification comprises deep semantic analysis (DSA) and formal methods. DSA is about understanding the purpose and intent of logic, flip-flops, state machines, etc. in a design, in the context of the verification objective being addressed. When this understanding is at the core of an EDA tool set, a major part of the sign-off process happens before the use or need of formal analysis. (more…)

Happy Holi: Spring Festival of Colors

Thursday, March 5th, 2015

This weekend on March 7, there will be Holi celebrations throughout San Jose and Silicon Valley.   In a celebration of spring that first started in India, young people gather to throw colored powders on each other, and often water is used to smear the colors as well.

holi-stanford

Holi Festival at Stanford University Campus, sponsored by Asha for Education

I have taken part several times with friends who grew up in India.  It is a lot fun and the food and sweets are excellent.  One popular celebration will be in Milpitas on March 7.  You can find all the details here.

Happy Holi!

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