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Archive for 2014

Redefining Chip Complexity in the SoC Era

Thursday, April 3rd, 2014

I am old enough to recall the Pentium versus AMD processor rivalry of 1990’s. Back then, the chip complexity was all about number of transistors and clock speed. More and more complex Pentiums were reeling out of factory at a pace, faster than we replaced dress shirts in our closets!

In today’s SoC, complexity is not just about clock speed or number of transistors packed in tiny wafers. We don’t hear much about clock speed of processor in the Apple iPhone, or the Samsung Galaxy 4 smartphone, do we?

Are we building less complex chips? Have our applications become simpler?

Quite the opposite. (more…)

X-Verification: A Critical Analysis for a Low-Power World (Video)

Thursday, March 27th, 2014

The problem logic designers have with X’s is that RTL simulation is optimistic in behavior and this can hide real bugs in your design when you go to tapeout.  Some engineers point out that we have always had to deal with X’s and nothing has really changed.

In fact, today’s SoC employ different power management schemes that wake-up or suspend IP.  As any designer knows, when powering up logic, any X’s must be cleared on reset or within a specific short number of cycles afterword.   The situation is now much more uncertain for designers whether all possible power scenarios are considered and all X’s will be cleared correctly.

Sorting all of this out with your simulator is too much and will be too late in the design process.  So, the temptation is to supply a reset to all the flops in your design, but this will be costly in terms of precious routing density and power usage. Ideally, you would have a static tool that could analyze the rest scheme of your design and then suggest a minimum sub-set of flops that need reset lines.  This week, on March 25, Real Intent unveiled major enhancements in its  Ascent XV product for early detection and management of unknowns (X’s) in digital designs, which address this issue. (more…)

RTL SOC Verification Goes Better with Synopsys VCS and Verdi

Thursday, March 20th, 2014

Real Intent will exhibit its Ascent™ and Meridian™ products for advanced SoC sign-off at the SNUG® Designer Community Expo (DCE) – part of the Synopsys® Users Group (SNUG) Silicon Valley event March 24-26 – and also will make a presentation at the first Verdi Interoperable Apps (VIA) Developers Forum there. At the DCE, Real Intent will showcase its Meridian CDC and Ascent XV working with Synopsys’ industry-leading VCS® verification solution as a part of the IC Verification community.  Real Intent’s Ascent products find elusive bugs and eliminate sources of uncertainty that are difficult to uncover using traditional Verilog or VHDL simulation, leading to both improved QoR and productivity of design teams. Meridian products accelerate sign-off verification of clock domain crossings and SDC in 500+M gate SoC designs.

At the VIA Developers Forum, myself and Mathew Yee, Sr. Application Engineer will present and highlight the features and benefits of Real Intent’s product integration with the comprehensive Verdi debug environment and its application to particular debug challenges such as clock domain crossing (CDC) verification. (more…)

Engineers Have Spoken: Design And Verification Survey Results

Thursday, March 13th, 2014

This blog was originally published in SemiEngineering.com and I wanted to make sure EDACafe readers saw it as well.  I have also added some more content versus the original.  Enjoy!

Previously I have blogged about the verification surveys that Real Intent runs at tradeshows throughout the year.  We find it useful to track trends in tool needs and reveal what are the pain points designers are feeling.  I last reported to you, a year ago, in the blog article Clocks and Bugs, where I focused on clock-domain crossing (CDC) errors causing re-spins.

This year, I would like to add some additional highlights and trends that I see from new survey data.

(more…)

New Ascent IIV Release Delivers Enhanced Automatic Verification of FSMs

Thursday, March 6th, 2014


Chris Morrison, Chief Architect at Real Intent, speaks with Graham Bell, about the new 2014 release of the Ascent IIV automatic formal verification product. They discuss the trends in automatic formal verification, the new finite-state machine (FSM) checks in the release, what makes Ascent IIV unique in the marketplace, and lastly, customer experience with the tool. (more…)

DVCon Panel Drill Down: “Where Does Design End and Verification Begin?” – Part 3

Thursday, February 27th, 2014

At last year’s Design and Verification Conference (DVCon) in San Jose, Real Intent sponsored a panel on “Where Does Design End and Verification Begin?”  In this Part 3 we are continuing with the questions from the moderator and answers by the panelists.

The panel was moderated by Brian Hunter, Cavium, Inc. and panelists:

Pranav Ashar – Real Intent, Inc.
John Goodenough – ARM, Inc.
Harry Foster – Mentor Graphics Corp.
Oren Katzir – Intel Corp.
Gary Smith – Gary Smith EDA

Below are links into the video recording where the question is asked and the immediate replies and comments by the panelists.  Starting with Questions 15 the panelists shared several interesting insights about gaps with verification test-sets, and higher level modeling and had a lot of back and forth with the other members. (more…)

DVCon Panel Drill Down: “Where Does Design End and Verification Begin?” – Part 2

Thursday, February 20th, 2014

At last years Design and Verification Conference (DVCon) in San Jose, Real Intent sponsored a panel on “Where Does Design End and Verification Begin?”  In this Part 2 we are continuing with the questions from the moderator and answers by the panelists.

The panel was moderated by Brian Hunter, Cavium, Inc. and panelists:

Pranav Ashar – Real Intent, Inc.
John Goodenough – ARM, Inc.
Harry Foster – Mentor Graphics Corp.
Oren Katzir – Intel Corp.
Gary Smith – Gary Smith EDA

Below are links into the video recording where the question is asked and the immediate replies and comments by the panelists.  The end-user insights by Goodenough from ARM and Katzir from Intel are particularly interesting. (more…)

DVCon Panel Drill Down: “Where Does Design End and Verification Begin?” – Part 1

Thursday, February 13th, 2014

At last years Design and Verification Conference (DVCon) in San Jose, Real Intent sponsored a panel on “Where Does Design End and Verification Begin?”

The panel was moderated by Brian Hunter, Cavium, Inc. and panelists:

Pranav Ashar – Real Intent, Inc.
John Goodenough – ARM, Inc.
Harry Foster – Mentor Graphics Corp.
Oren Katzir – Intel Corp.
Gary Smith – Gary Smith EDA

Brian opened the panel with the following remarks and then asked a series of questions.  Below are links into the video recording where the question is asked and the immediate replies and comments by the panelists.  If you don’t have time to listen for the full 20 minutes, jump down to Questions 6, 7 and 8 to see the highlights for part 1.  Next week we present part 2.

(Brian Hunter begins) Our topic today is the blurring lines between design and verification. Most people know that verification schedules are the long pole and getting too long and we need designers to take on a larger role in the verification process. (more…)

Video Tech Talk: Changes In Verification

Thursday, February 6th, 2014

Ed Sperling, Editor-in-Chief of SemiEngineering.com spoke with Dr. Roger B. Hughes, Director of Strategic Accounts at Real Intent, about what’s changing in verification as design complexity increases and where engineers typically make mistakes.

Progressive Static Verification Leads to Earlier and Faster Timing Sign-off

Thursday, January 30th, 2014

I originally wrote and posted this blog here on SOCcentral.com.  It is reproduced below.

January 22, 2014 — As SOC design crosses the billion-gate threshold the cost of errors grows dramatically. The demand that engineers ensure their work is as correct as possible — and as soon as possible — in the design process has become more insistent. Letting errors slip forward one stage closer to implementation means their impact will grow while their causes become obscured and success is delayed. The design sign-off process itself has grown more complex, and the register-transfer level (RTL) is now where sign-off begins.

A starting point for the sign-off regimen is verification of the timing behavior of the heterogeneous IP used in an SOC and how the IP interfaces with the host design, including how clocks and signals cross any interfaces. Clocking schemes must be defined to enable earlier static analysis before it reaches the simulation stage. However, before timing analysis and simulation begin, designs must be cleaned using Lint tools.

Modern Lint tools have evolved to the point where they can handle full-chip designs and yet still offer concise hierarchical reporting. The availability of low-noise reporting means less time waiving violations and more time cleaning easy-to-fix issues. Because of the lower-noise, designers can use the tool earlier and more often. However, an RTL Lint tool requires only rule-setup and, therefore, cannot provide a deep analysis.

(more…)

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