Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
P2415 – New IEEE Power Standard for Unified Hardware Abstraction
December 4th, 2014 by Graham Bell
The IEEE announced in September that is was launching working a on a new power standard called P2415. This blog gives the background for this new effort.
The current low power design and verification standard (IEEE 1801-2013 and IEEE P1801) is focused on the voltage distribution structure in design at Register Transfer Level (RTL) description and below. It has minimal abstraction for time (having only an interval function for modeling clock frequency), but depends on other hardware oriented standards to abstract events, scenarios, clock trees, etc. which are required for energy proportional design, verification, modeling and management of electronic systems. The necessary abstractions of hardware, as well as layers and interfaces in software are not yet defined by any existing standards.
The energy design and management flow for electronic devices is disconnected among different stages of the design process and lacks the abstractions, formats, interfaces, and automated methodologies long established and standardized in functional design and verification of hardware and software for electronic systems. The main disconnects on energy issues are at the handover points between various design teams:
The new P2415 standard has the goal to remove the above disconnects and lead to a well-connected energy oriented design flow enabling energy proportionality as the main design principle. It addresses energy proportionality through tight interplay between energy-oriented hardware and energy-aware software. It provides new design, verification, modeling, management and testing abstractions and formats for hardware, software and systems to model energy proportionality, and enables the design methodology that naturally follows the top-down approach – from the system and software down to the hardware.
The new standard defines the syntax and semantics for energy oriented description of hardware, software and power management for electronic systems. It enables specifying, modeling, verifying, designing, managing, testing and measuring the energy features of the device, covering both the pre- and post-silicon design flow.
On the hardware side the description covers enumeration of semiconductor intellectual property components (System on Chip, board, device), memory map, bus structure, interrupt logic, clock and reset tree, operating states and points, state transitions, energy and power attributes. On the software side the description covers software activities and events, scenarios, external influences (including user input) and operational constraints; and on the power management side the description covers activity dependent energy control.
The new standard, once completed and approved, will be intended to be compatible with the current IEEE 1801™-2013 (UPF) standard to support an integrated design flow. Additionally, the new standard would complement functional models in standard hardware description languages IEEE 1076™ (VHDL), IEEE 1364™ (Verilog), IEEE 1800™ (SystemVerilog), and IEEE 1666™ (SystemC), by providing an abstraction of the design hierarchy and an abstraction of the design behavior with regard to power and energy usage.
“IEEE P2415 will provide the higher level of energy abstraction for the system-on-chip and the whole device and, therefore, will enable earlier (more abstract) modeling of power states using the IEEE 1801-2013 (UPF) standard,” said Dr. Vojin Zivojnovic, chair of the IEEE P2415 working group and CEO of Aggios, Inc. “Many software engineers and system architects will find this effort well-aligned with their need to communicate their low-power and energy requirements with the hardware engineers in an aligned fashion for holistic, quantifiable and reusable energy optimizations. I welcome them to participate in this industry-wide effort.”
To participate in the new working group you can contact Dr. Zivojnovic at the following email: vojin.zivojnovic [at] aggios.com
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