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 Real Talk

Archive for November, 2014

The Evolution of RTL Lint

Thursday, November 27th, 2014

This article was originally published on TechDesignForums and is reproduced here by permission.

It’s tempting to see lint in the simplest terms: ‘I run these tools to check that my RTL code is good. The tool checks my code against accumulated knowledge, best practices and other fundamental metrics. Then I move on to more detailed analysis.’

It’s an inherent advantage of automation that it allows us to see and define processes in such a straightforward way. It offers control over the complexity of the design flow. We divide and conquer. We know what we are doing.

Yet linting has evolved and continues to do so. It covers more than just code checking. We begun with verifying the ‘how’ of the RTL but we have moved on into the ‘what’ and ‘why’. We use linting today to identify and confirm the intent of the design.

A lint tool, like our own Ascent Lint, is today one of the components of early stage functional verification rather than a precursor to it, as was once the case.

At Real Intent, we have developed this three-stage process for verifying RTL: (more…)

Parallelism in EDA Software – Blessing or a Curse?

Thursday, November 20th, 2014

To satisfy demands for lower-power and higher performance, the use of multiple CPU cores is a norm in SoC design.  The interaction of multiple cores and the surrounding semiconductor IP, presents new challenges to verification.  But what about EDA tool providers?  How can the use of multple CPUs improve performance and throughput in their tools?  What software caveats do they need to be aware to support processing by parallel CPUs?  Pranav Ashar, CTO at Real Intent gives his perspective below.

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EDA tools must be exploit parallelism to keep up with SoC complexity, or we will be attempting to designing next-generation chips on what effectively will be antique hardware.

A couple of factors have combined to reduce the pace at which parallelism has been adopted in EDA tools. It is common to overlook the latency impact when designing parallel programs that communicate with physical memory.  Cache-coherency and memory access latency are often encountered examples that lowers the processing throughput of a tool on a multi-core processor.  Fine-grain multi-threading in EDA tools quickly triggers some of these latency bottlenecks – for the typical SoC benchmark, these limits are reached rather rapidly.

(more…)

How Big is WWD – the Wide World of Design?

Thursday, November 13th, 2014

Its a fact of life that semiconductor design is a world-wide activity, and that EDA companies are helping customers in a 24 hour day. How international is this world? According to the latest statistics from the EDA Consortium, over 50% of the business activity is outside North America.  The total of EDA, semiconductor IP and design services revenue was 6.9 billion dollars in 2013.  Comparing this to a world population of 7.1 billion means roughly one dollar per person was spent on the wide world of design.

EDA and SIP distribution

Fig. 1. Distribution of World-Wide EDA, IP and Services Revenue (EDA Consortium)

(more…)

CMOS Pioneer Remembered: John Haslet Hall

Thursday, November 6th, 2014

I still get the daily newspaper delivered to my house, the San Jose Mercury News.   I came across the obituary for John Haslet Hall, one of the leading innovators at the birth of CMOS technology in Silicon Valley.  I had not heard of Hall, and thought that you might also want to learn of his many wide-ranging contributions to the world of semiconductors.


John Haslet HallJohn Haslet Hall, son of the late William McLaurine Hall, Jr and Mary Helen (Ent) Hall, was born July 11, 1932 and died October 30, 2014.

Hall was an early and prolific Silicon Valley inventor. In a career that spanned over 60 years, Hall developed technology included in over 20 fundamental patents, including pioneering work in low-power CMOS integrated circuit technology. A 1992 San Francisco Chronicle article referred to Hall as, “one of Silicon Valley’s unsung innovators.”
Hall served in the U.S. Navy in the late 1950s, working with aircraft electronics development and testing, often riding in planes that were pulling target drones to collect data. He graduated from the University of Cincinnati in 1961 and sought to apply his chemical engineering education in the nascent semiconductor industry.

(more…)

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