Ramesh is VP of Product Strategy at Real Intent. He brings 25+ years of experience in engineering, customer management, product management and marketing to Real Intent. Prior to joining Real Intent, he led the product marketing of the core product suite related to RTL design at Atrenta. Previously, … More »
DVClub Shanghai: Making Verification Debug More Efficient
October 23rd, 2014 by Ramesh Dewangan
DVClub Shanghai took place on Sept. 26, 2014 with presentations by Real Intent, Solvertec, Mentor Graphics, Cadence, Synopsys and ARM. The theme of the meeting was “Making Verification Debug More Efficient.” Before I talk about two of the presentations that were recorded, here is some quick background on DVClub Shanghai which started at the end of 2013.
It was initiated by
The principle goal of DVClub is to have fun while helping build the verification community through quarterly educational and networking events. The DVClub events are targeted to the semiconductor industry in China, with a focus on design verification. Membership is free and is open to all non-service provider semiconductor professionals. Most members work in verification, but there are also plenty of entrepreneurs, students, managers, investors, and even design engineers who attend. There are at least 4 events every year: March, June, September and December.
Mike Bartley opened the event with a talk that was titled “Improving Debug – Our biggest Challenge?” If you follow the link you can see the recording of his presentation, where he talks about the 6 things that we need for improved debug.
My presentation was on “Shortening Debug with New Methods in Static Verification.“
Even with high degree of design reuse, verification continues to be the long pole in design development. This has created a huge stress in current functional verification methodologies, which rely primarily on dynamic verification. Design complexity has made debug cycle times unpredictable and longer.
Static verification is a perfect complement to the dominantly dynamic verification in use today. Not only is static verification exhaustive, it needs minimal setup and offers faster debug cycles. Both structural and formal techniques have made dramatic advances in the recent years by analyzing the designer’s intent. Structural static verification has expanded its effectiveness to several critical application domains. And formal techniques have progressed from an expert-user model to a mainstream-user model.
The static verification techniques have been successfully used in targeted problem domains like clock domain crossing, reset optimization, X-optimism/pessimism, FSM integrity and so on. My presentation provides specific design examples and how the static techniques solves them more efficiently.
Not every verification problem is a nail that you need big hammer for. Simulation is too expensive and time consuming for a majority of verification problems. Why not, ease the pain by using faster, targeted, and exhaustive static verification techniques to shorten your verification debug cycle?
And to everyone from India, Shubh Diwali!