Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
Fundamentals of Clock Domain Crossing Verification: Part Two
July 17th, 2014 by Graham Bell
Last time we looked at how metastability is unavoidable and the nature of the clock domain crossing (CDC) problem. This time we will look at design principles.
CDC design principles
Because metastability is unavoidable in CDC designs, the robust design of CDC interfaces is required to follow some strict design principles.
Metastability can be contained with “synchronizers” that prevent metastability effects from propagating into the design. Figure 9 shows the configuration of a double-flop synchronizer which minimizes the load on the metastable flop. The single fan-out protects against loss of correlation because the metastable signal does not fan out to multiple flops. The probability that metastability will last longer than time t is governed by the following equation:
where tau is the resolution time constant dependent upon the latch characteristics and ambient noise. This configuration resolves metastability with a very high probability, leading to a very large mean time between failures as governed by the equation:
where P is the probability that metastability is not resolved within one clock cycle. Triple or higher flop configurations may be used for very fast designs.
Designing CDC interfaces
A CDC interface is designed for reliable transfer of correlated data across the data bus and the reliable design of a CDC interface must follow a simple set of rules:
These principles can be implemented using handshake protocols or FIFO-based protocols. Figure 10 shows a simple handshake CDC protocol. This interface is transmitting data from CLK1 domain to CLK2 domain. While Data Ready is asserted, the data on the bus Data In is transmitted across the clock domain. The data availability is signaled by a transition on Control Signal. Transmit Data is launched on the same clock edge. Control Signal is synchronized in the CLK2 domain and the transition is detected to signal Load Data. Since, synchronization requires at-least one cycle of CLK2, Transmit Data is received at the second edge of CLK2 or later. This creates a multi-cycle path for Transmit Data across the interface. Feedback Signal completes the handshake.
Transition on Feedback Signal is detected to drive Next Data to the interface. Figure 11 shows the timing diagram for the protocol. It should be noted that this is a simplified concept of the interface. We have not incorporated the logic initializing the interface, detecting transition in Data Ready and dealing with stalling conditions. All these considerations, combined with latency minimization, add complexity to the design of the interface.
Next time we will start the discussion on verifying CDC interfaces.