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Dr. Pranav Ashar
Dr. Pranav Ashar
Dr. Pranav Ashar is chief technology officer at Real Intent. He previously worked at NEC Labs developing formal verification technologies for VLSI design. With 35 patents granted and pending, he has authored about 70 papers and co-authored the book ‘Sequential Logic Synthesis’.

Reset Optimization Pays Big Dividends Before Simulation

 
June 26th, 2014 by Dr. Pranav Ashar

This article was originally published on TechDesignForums and is reproduced here by permission.

Reset optimization is another one of those design issues that has leapt in complexity and importance as we have moved to ever more complex system-on-chips. Like clock domain crossing, it is one that we need to resolve to the greatest degree possible before entering simulation.

The traditional approach to resets might have been to route to every flop. Back in the day, you might have been done this even though it has always entailed a large overhead in routing. That would help avoid X ‘unknown’ states arising during simulation for every memory location that was not reinitialized at restart. It was a hedge against optimistic behavior by simulation that could hide bugs.

Our objectives today, though, include not only conserving routing resources but also capturing problems as we bring up RTL for simulation to avoid unfeasible run times there at both RTL and – worse still – the gate level.

There is then one other important factor for reset optimization: its close connection to power optimization.

Matching power and performance increasingly involves the use of retention cells. These retain the state of elements of the design even if appears to be powered off: in fact, to allow for a faster restart bring-up these must continue to consume static power even when the SoC is ‘at rest’. So, controlling the use of retention cells cuts power consumption and extends battery life.

Reset the ‘endless’ threat

Resolving such complex issues based purely on simulations will no longer work. It will put you on the path toward so-called ‘endless verification’.

A thorough and intelligent pre-simulation analysis of your reset scheme can now point both to the best reset routing and the minimum number of expensive retention cells you need to implement.

At the pre-simulation stage, tools like Ascent XV from my company Real Intent, can undertake a pretty smart heuristic analysis of the dependency of one flop’s reset on another and the relationships between different blocks. They will then produce a report with further insights and characterization, based on formal and structural techniques, that go some way beyond just ‘a best guess’.

The objective is to inform the designer on either the specifics or the flavor of the potential problems in the design. He can then review this report – which ideally should offer some alternatives itself – and undertake reset and related power optimization before moving into full simulation.

Orders of magnitude do apply

The time-savings available are significant. Unresolved reset issues lead, of course, to X states, uncertainties post-simulation that will take considerable time to address. The familiar ‘Rule of 10’ applies: catch a problem earlier and it is a 10X easier fix.

Beyond that, pre-simulation techniques are becoming more powerful with each generation. Our latest release of Ascent XV has enhanced algorithms that in themselves offer a 10X improvement in run-time against the previous generation.

Preparing your code carefully for simulation has a direct benefit at the bottom line by leveraging increasingly mature strategies. Can you afford not to consider them within your flow?

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2 Responses to “Reset Optimization Pays Big Dividends Before Simulation”

  1. Ryan O'Connor says:

    We recently came across a cell based architecture for an IC in regards to power routing in standard cell <a href="www.911eda.com" "PCB designs". In this architecture, there is a row of cell instances bordering a first adjacent row of cell instances along a first boundary and a second adjacent row of cell instances along a second boundary. A first power rail (e.g., carrying an auxiliary voltage) extends along the first boundary. A second power rail (e.g., VSS) extends along the second boundary. The second power rail is wider than the first power rail. Additionally, a third power rail (e.g., VDD) extends across the interior of the second row of cells. Have you seen a design using this type of architecture?

  2. Graham Bell Graham Bell says:

    Ryan,
    No I have not seen such a power routing architecture.
    Best
    +Graham

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