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Archive for June, 2014

Reset Optimization Pays Big Dividends Before Simulation

Thursday, June 26th, 2014

This article was originally published on TechDesignForums and is reproduced here by permission.

Reset optimization is another one of those design issues that has leapt in complexity and importance as we have moved to ever more complex system-on-chips. Like clock domain crossing, it is one that we need to resolve to the greatest degree possible before entering simulation.

The traditional approach to resets might have been to route to every flop. Back in the day, you might have been done this even though it has always entailed a large overhead in routing. That would help avoid X ‘unknown’ states arising during simulation for every memory location that was not reinitialized at restart. It was a hedge against optimistic behavior by simulation that could hide bugs.

Our objectives today, though, include not only conserving routing resources but also capturing problems as we bring up RTL for simulation to avoid unfeasible run times there at both RTL and – worse still – the gate level.

There is then one other important factor for reset optimization: its close connection to power optimization.

Matching power and performance increasingly involves the use of retention cells. These retain the state of elements of the design even if appears to be powered off: in fact, to allow for a faster restart bring-up these must continue to consume static power even when the SoC is ‘at rest’. So, controlling the use of retention cells cuts power consumption and extends battery life. (more…)

SoC CDC Verification Needs a Smarter Hierarchical Approach

Thursday, June 19th, 2014

This article was originally published on TechDesignForums and is reproduced here by permission.

Thanks to the widespread reuse of intellectual property (IP) blocks and the difficulty of distributing a system-wide clock across an entire device, today’s system-on-chip (SoC) designs use a large number of clock domains that run asynchronously to each other. A design involving hundreds of millions of transistors can easily incorporate 50 or more clock domains and hundreds of thousands of signals that cross between them.

Although the use of smaller individual clock domains helps improve verification of subsystems apart from the context of the full SoC, the checks required to ensure that the full SoC meets its timing constraints have become increasingly time consuming.

Signals involved in clock domain crossing (CDC), for example where a flip-flip driven by one clock signal feeds data to a flop driven by a different clock signal raise the potential issue of metastability and data loss. Tools based on static verification technology exist to perform CDC checks and recommend the inclusion of more robust synchronizers or other changes to remove the risk of metastability and data loss.


Photo Booth Blackmail at DAC in San Francisco!

Thursday, June 12th, 2014

Real Intent had a photo booth at its exhibit in San Francisco at the Design Automation Conference.  We thought it would be cool to give a photo souvenir of the 51st conference for anyone who strolled by and to celebrate the 2014 FIFA World Cup.  On hand to work the booth was Jeremy who helped everyone with funny props or choosing the right World Cup team jersey.

Between Jeremy and myself we were able to get some great photos.  Here are just a few for your viewing pleasure.   And at the bottom of the page, you can click on the link to see all the blackmail photos for your fellow conference attendees and exhibitors.   Enjoy!

Happy Patriot!


Quick Reprise of DAC 2014

Thursday, June 5th, 2014

Thanks to everyone that came to the 2014 Design Automation Conference.  It was a successful show with maximum traffic on Tuesday afternoon.  At the Real Intent booth we were giving away Roses (yes they were real!) and had a photo booth as well.   Visitors could dress up in world-cup soccer jerseys and hoist the World Cup 2014 Trophy.

IMG_0316 (more…)

S2C: FPGA Base prototyping- Download white paper

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