Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
Next Generation of Static RTL Sign-off
May 22nd, 2014 by Graham Bell
Years ago when Real Intent began, 10 million logic gate designs were considered “top of the line.” Today you might be dealing with billion-gate designs – significantly more complicated across a far wider scope of applications. The sheer complexity leads to a whole new host of verification challenges. Because sign-off is an iterative process, you have to deal with things like capacity, performance, power and timing issues, and engineering effort at each step. There’s a real need for toolsets that handle functional verification tasks prior to simulation and synthesis to avoid the exorbitant cost of silicon failure – so much so, that even Synopsys is getting onboard with a new verification suite.
Real Intent is committed to deliver the industry’s best possible software tools for verifying next-generation digital designs for FPGAs and complex SoCs. Our Ascent products for static functional verification prior to synthesis, and our Meridian products for advanced sign-off verification for CDC and constraints timing, uniquely address specific SoC sign-off issues. They save design and verification engineers a lot of time and effort, and give 10x better design quality and productivity compared to alternative methods. We also work closely with industry leaders like Defacto, Calypto and our newest industry partner, MathWorks, to ensure quality and compatibility.
In our product set you’ll find the industry’s fastest and lowest-noise RTL lint solution; automatic detection of up to 50-percent of design functional errors prior to testbench development and simulation; a way to find and isolate X-propagation issues and make your designs X-safe right from power-on reset; the fastest, highest capacity and most precise CDC solution that enables all aspects of CDC sign-off.
We constantly strive for technical advancements that help you succeed. For example, our newly announced version of Ascent Lint adds 24 new lint rules and other significant enhancements, and tightly integrates Ascent Lint within MATLAB® to promote a safe and reliable implementation flow for digital synthesis tools used by ASIC and FPGA designers. Now they can verify that the RTL code generated using HDL Coder is compliant with their coding conventions and industry standards.
Come visit us in Booth #1825 at DAC next month. You’ll see how our focus last year on re-engineering our Ascent and Meridian tools for comprehensive, unsurpassed verification and sign-off support is paying off for companies this year. And for fun, you also can pick up your “Passport to Innovation.” Just get it stamped by Calypto, DeFacTo, MathWorks and Real Intent, and you’ll arrive at your destination – entry in a drawing for $100 Amazon gift cards and a 10″ Android tablet. I look forward to seeing you at DAC!