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Archive for May 22nd, 2014

Next Generation of Static RTL Sign-off

Thursday, May 22nd, 2014

Years ago when Real Intent began, 10 million logic gate designs were considered “top of the line.” Today you might be dealing with billion-gate designs – significantly more complicated across a far wider scope of applications. The sheer complexity leads to a whole new host of verification challenges. Because sign-off is an iterative process, you have to deal with things like capacity, performance, power and timing issues, and engineering effort at each step. There’s a real need for toolsets that handle functional verification tasks prior to simulation and synthesis to avoid the exorbitant cost of silicon failure – so much so, that even Synopsys is getting onboard with a new verification suite.

Real Intent is committed to deliver the industry’s best possible software tools for verifying next-generation digital designs for FPGAs and complex SoCs. Our Ascent products for static functional verification prior to synthesis, and our Meridian products for advanced sign-off verification for CDC and constraints timing, uniquely address specific SoC sign-off issues. They save design and verification engineers a lot of time and effort, and give 10x better design quality and productivity compared to alternative methods. We also work closely with industry leaders like Defacto, Calypto and our newest industry partner, MathWorks, to ensure quality and compatibility.

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DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL



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