Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog Assertions
May 1st, 2014 by Graham Bell
Its only one month left until the Design Automation Conference in San Francisco, June 1-5 and the process of getting ready is keeping me BUSY. This week, I would like to highlight the DVCon 2014 Best Oral Presentation by Kelly D. Larson from NVIDIA on “Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog Assertions.”
This paper describes an entirely different way to use these same SVA assertions. While the standard use of SystemVerilog assertions is typically targeted towards DESIGN QUALITY, this paper describes how to effectively use assertions to target individual TEST QUALITY. In many cases the same SystemVerilog assertions which were written for measuring design quality can also be used to measure test quality, but it’s important to realize that the fundamental goal is quite different.
The PowerPoint slides for Kelly’s presentation are here and are excellent in explaining the intent.
Reproduced below is the paper outlining Kelly’s talk.