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Archive for May 1st, 2014

Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog Assertions

Thursday, May 1st, 2014

Its only one month left until the Design Automation Conference in San Francisco,  June 1-5 and the process of getting ready is keeping me BUSY.   This week, I would like to highlight the DVCon 2014 Best Oral Presentation by Kelly D. Larson from NVIDIA on “Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog Assertions.

This paper describes an entirely different way to use these same SVA assertions. While the standard use of SystemVerilog assertions is typically targeted towards DESIGN QUALITY, this paper describes how to effectively use assertions to target individual TEST QUALITY. In many cases the same SystemVerilog assertions which were written for measuring design quality can also be used to measure test quality, but it’s important to realize that the fundamental goal is quite different. (more…)

Naked and Afraid – THE SEARCH FOR CAPITAL, Mon. May 5

Thursday, May 1st, 2014

Whether you are an entrepreneur or even thought about being one, you know that there are two things to worry about – time and money.

Everyone is welcome at the upcoming installment of the popular EDAC – Jim Hogan Emerging Companies Series, where Jim and other panelists (Amit Gupta, President and CEO, Solido Design Automation, Inc. and Vishal Kapoor, Principal, Three Legged Stool, LLC.) will discuss the sources of money – from crowdfunding to institutional investment to intrapreneural capital. The panel will debate the opportunities and risks associated with those sources and which one might be right for you.

Every entrepreneur believes that they know their product, but often only from a technical capability perspective. How you position, communicate and sell your product may be more important than it’s underlying capability. Without having a keen understanding of what you are building, how capital efficient it is and who needs it, the chances of getting that capital are significantly diminished.


S2C: FPGA Base prototyping- Download white paper

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