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Archive for April 24th, 2014

Complexity Drives Smart Reporting in RTL Verification

Thursday, April 24th, 2014

This article was originally published on TechDesignForums and is reproduced here by permission.

It’s an increasingly complex world in which we live and that seems to be doubly true of state-machine design.

With protocols such as USB3, PCI Express and a growing number of cache coherent multiprocessor on-chip buses and networks, the designer has been greeted with a state-space explosion. USB3 has, for example, added an entire link layer and, with it, the Link Training and Status State Machine. This is, in itself, a complex entity, which although it has only 12 states in total can move between them using a variety of different arcs. (more…)

S2C: FPGA Base prototyping- Download white paper

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