Recently, we have seen announcements by the Big Three EDA Companies about new initiatives in the area of SoC verification. Synopsys for example, has started talking about Verification Compiler and how it is introducing static and formal checks for the first time, and relies on the Verdi debugging environment (acquired from SpringSoft) to tie it all together. Real Intent has been delivering solutions focused static and formal for several years now (and also relies on Verdi for Debug). The industry really started taking notice of this static verification trend in 2013 at DVCon and we have seen it grow through DAC 2013 in Austin. We are now talking about designs crossing the billion-gate threshold and what can be done to not only control this explosion of complexity, but also to achieve sign-off for RTL code.
RTL and gate-level simulation theoretically can be used to fully test a billion-gate SoC, but the cost of complete RTL testing is beyond what design teams can afford. To reduce the testing cost and the risk of missing critical tests, abstract modeling and pre-simulation static analysis of RTL have now become imperative in SoC design flows. Integration of heterogeneous IP and design units require confirmation of protocols, power budgets, testability and the correct operation of multiple interfaces and clock domain crossings (CDC).