Open side-bar Menu
 Real Talk
Ramesh Dewangan
Ramesh Dewangan
Ramesh is VP of Product Strategy at Real Intent. He brings 25+ years of experience in engineering, customer management, product management and marketing to Real Intent. Prior to joining Real Intent, he led the product marketing of the core product suite related to RTL design at Atrenta. Previously, … More »

Redefining Chip Complexity in the SoC Era

April 3rd, 2014 by Ramesh Dewangan

I am old enough to recall the Pentium versus AMD processor rivalry of 1990’s. Back then, the chip complexity was all about number of transistors and clock speed. More and more complex Pentiums were reeling out of factory at a pace, faster than we replaced dress shirts in our closets!

In today’s SoC, complexity is not just about clock speed or number of transistors packed in tiny wafers. We don’t hear much about clock speed of processor in the Apple iPhone, or the Samsung Galaxy 4 smartphone, do we?

Are we building less complex chips? Have our applications become simpler?

Quite the opposite.

We are building chip with complexity that is orders of magnitude higher than the past. The definition of complexity is changing though. Whereas there are still old measures in play like lower process nodes and size, many more attributes now determine your SoC complexity.

First let’s acknowledge, we continue to have to deal with packing huge number of transistors into tiny wafers. Look at the sheer size of some of the popular consumer devices. In the techreport.com1 article, published in Aug. 2013, it was revealed at the Hot Chips conference that Xbox One’s AMD-designed SoC, employing eight Jaguar CPU cores and GCN-class integrated graphics, is 363 mm² in area and is comprised of roughly 5 billion transistors; and produced at TSMC on a 28-nm process. Comparable in size, the AMD Tahiti GPU that powers the Radeon HD 7970 is also produced on a 28-nm process at TSMC, and Tahiti packs 4.3 billion transistors into 365 mm². Nvidia’s GK110 GPU, also made on TSMC’s 28-nm process, has 7.1 billion transistors and is 551 mm².  These are big chips!

We continue to have to march towards lower nodes to meet the performance and capacity demands on today’s chips for the applications in mobile, gaming, automotive, cloud computing and others. According to EETimes2, quoting Aart de Geus of Synopsys, the respected EDA industry leader, the tapeouts on advanced node continue to rise:

Number of Tapeouts Per Process Node (per Synopsys, Inc.)

So, what’s new?

For one, today’s SoCs have high degree of re-use and integration of multiple IPs. Look at the variety of functions our smartphones perform! Here is a typical application processor from VIA as per tgdaily3:

Typical Application Processor for a Smartphone (courtesy VIA, Inc.)

We needed multiple chips to perform that amount of function in the past. Yesterday’s SoCs have become todays’ IPs. Now we have multiple IPs taking care of diverse functions, integrated into a single SoC. No wonder, according to same EETimes2 report, IP reuse is to rise significantly as we go towards more complex chips needing lower nodes:

Increase of IP Reuse with Semiconductor Process Node (courtesy of International Business Strategies)

What that means is that IPs need to be signed off with a rigorous methodology before integration, and there must be a sound methodology for the IPs to be integrated smoothly in the SoCs. This methodology must account for clocks, clock domains, timing constraints, low power and test structures, between the IPs and between IPs and SoC.

The consumer mobile revolution brings more critical design challenges, e.g. the proliferation of low-power and asynchronous interfaces. Low power requirements have become acute to ensure the longest possible life for a smartphone customer. As a result we see the number of voltage domains and power domains have gone up rapidly. Similarly, the rise in asynchronous IP components within a chip means the number of asynchronous clocks and clock domains are higher than the past and can exceed 100 in number. You have to not only ensure the asynchronous clock domain crossings are properly synchronized, but also address the risk of any signal glitches that will be missed in simulation.

These new attributes of chip complexity are going to explode with the arrival of Internet of things. In a recent Gartner4 report, it forecast there will be nearly 26 billion devices on the Internet of Things by 2020, and according to ABI Research there will be more than 30 billion devices wirelessly connected by that time.

Our dress shirts may still be getting replaced at the same pace as in the past, but we need new methodologies and techniques to reel out today’s chip at a significantly faster pace!



Related posts:

One Response to “Redefining Chip Complexity in the SoC Era”

Leave a Reply

Your email address will not be published. Required fields are marked *


You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <strike> <strong>

CST Webinar Series

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy