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Archive for April, 2014

Complexity Drives Smart Reporting in RTL Verification

Thursday, April 24th, 2014

This article was originally published on TechDesignForums and is reproduced here by permission.

It’s an increasingly complex world in which we live and that seems to be doubly true of state-machine design.

With protocols such as USB3, PCI Express and a growing number of cache coherent multiprocessor on-chip buses and networks, the designer has been greeted with a state-space explosion. USB3 has, for example, added an entire link layer and, with it, the Link Training and Status State Machine. This is, in itself, a complex entity, which although it has only 12 states in total can move between them using a variety of different arcs. (more…)

Video Update: New Ascent XV Release for X-optimization, ChipEx show in Israel, DAC Preview

Thursday, April 17th, 2014

I stopped in at EELive! show in San Jose on April 2, 2014 and spoke with Sanjay Gangal, President of Internet Business Systems and about the latest release of the Ascent XV X-verification system and its latest design reset optimization features. I also gave a preview of the activities at the ChipEx conference in Israel on April 30, 2014 and the Design Automation Conference in San Francisco on the dates of June 2-4, 2014.  Click on the picture to play the interview.


How the Heartbleed Bug Works

Wednesday, April 16th, 2014

The following is courtesy of the website and can be seen in its original form here:

Design Verification is Shifting Left: Earlier, Focused and Faster

Thursday, April 10th, 2014

Recently, we have seen announcements by the Big Three EDA Companies about new initiatives in the area of SoC verification.  Synopsys for example, has started talking about Verification Compiler and how it is introducing static and formal checks for the first time, and relies on the Verdi debugging environment (acquired from SpringSoft) to tie it all together.  Real Intent has been delivering solutions focused static and formal for several years now (and also relies on Verdi for Debug).  The industry really started taking notice of this static verification trend in 2013 at DVCon and we have seen it grow through DAC 2013 in Austin.   We are now talking about designs crossing the billion-gate threshold and what can be done to not only control this explosion of complexity, but also to achieve sign-off for RTL code.

RTL and gate-level simulation theoretically can be used to fully test a billion-gate SoC, but the cost of complete RTL testing is beyond what design teams can afford. To reduce the testing cost and the risk of missing critical tests, abstract modeling and pre-simulation static analysis of RTL have now become imperative in SoC design flows. Integration of heterogeneous IP and design units require confirmation of protocols, power budgets, testability and the correct operation of multiple interfaces and clock domain crossings (CDC).


Redefining Chip Complexity in the SoC Era

Thursday, April 3rd, 2014

I am old enough to recall the Pentium versus AMD processor rivalry of 1990’s. Back then, the chip complexity was all about number of transistors and clock speed. More and more complex Pentiums were reeling out of factory at a pace, faster than we replaced dress shirts in our closets!

In today’s SoC, complexity is not just about clock speed or number of transistors packed in tiny wafers. We don’t hear much about clock speed of processor in the Apple iPhone, or the Samsung Galaxy 4 smartphone, do we?

Are we building less complex chips? Have our applications become simpler?

Quite the opposite. (more…)

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