Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
X-Verification: A Critical Analysis for a Low-Power World (Video)
March 27th, 2014 by Graham Bell
The problem logic designers have with X’s is that RTL simulation is optimistic in behavior and this can hide real bugs in your design when you go to tapeout. Some engineers point out that we have always had to deal with X’s and nothing has really changed.
In fact, today’s SoC employ different power management schemes that wake-up or suspend IP. As any designer knows, when powering up logic, any X’s must be cleared on reset or within a specific short number of cycles afterword. The situation is now much more uncertain for designers whether all possible power scenarios are considered and all X’s will be cleared correctly.
Sorting all of this out with your simulator is too much and will be too late in the design process. So, the temptation is to supply a reset to all the flops in your design, but this will be costly in terms of precious routing density and power usage. Ideally, you would have a static tool that could analyze the rest scheme of your design and then suggest a minimum sub-set of flops that need reset lines. This week, on March 25, Real Intent unveiled major enhancements in its Ascent XV product for early detection and management of unknowns (X’s) in digital designs, which address this issue.
Lisa Piper, senior manager of technical marketing at Real Intent summarized the new release as follows: “Analysis and optimization of design reset and initialization is a new requirement for SoC sign-off due to the presence of X’s that can arise from modern power-management techniques. Ascent XV can ensure that the initialization sequences are complete and optimal for various power states in an SoC and identify only those areas of risk that need attention by the designer, ignoring trivial X’s. With this new release we are continuing to innovate to deliver best-in-class verification performance and debug efficiency.”
To hear why X’s in SoC designs are becoming more of a problem, what features in the new 2014 Ascent XV software release addresses these issues, why simulation is not up to the challenge and what is her favorite feature is in Ascent XV, please watch the video of Lisa Piper below.