The problem logic designers have with X’s is that RTL simulation is optimistic in behavior and this can hide real bugs in your design when you go to tapeout. Some engineers point out that we have always had to deal with X’s and nothing has really changed.
In fact, today’s SoC employ different power management schemes that wake-up or suspend IP. As any designer knows, when powering up logic, any X’s must be cleared on reset or within a specific short number of cycles afterword. The situation is now much more uncertain for designers whether all possible power scenarios are considered and all X’s will be cleared correctly.
Sorting all of this out with your simulator is too much and will be too late in the design process. So, the temptation is to supply a reset to all the flops in your design, but this will be costly in terms of precious routing density and power usage. Ideally, you would have a static tool that could analyze the rest scheme of your design and then suggest a minimum sub-set of flops that need reset lines. This week, on March 25, Real Intent unveiled major enhancements in its Ascent XV product for early detection and management of unknowns (X’s) in digital designs, which address this issue. (more…)