Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
RTL SOC Verification Goes Better with Synopsys VCS and Verdi
March 20th, 2014 by Graham Bell
Real Intent will exhibit its Ascent™ and Meridian™ products for advanced SoC sign-off at the SNUG® Designer Community Expo (DCE) – part of the Synopsys® Users Group (SNUG) Silicon Valley event March 24-26 – and also will make a presentation at the first Verdi Interoperable Apps (VIA) Developers Forum there. At the DCE, Real Intent will showcase its Meridian CDC and Ascent XV working with Synopsys’ industry-leading VCS® verification solution as a part of the IC Verification community. Real Intent’s Ascent products find elusive bugs and eliminate sources of uncertainty that are difficult to uncover using traditional Verilog or VHDL simulation, leading to both improved QoR and productivity of design teams. Meridian products accelerate sign-off verification of clock domain crossings and SDC in 500+M gate SoC designs.
At the VIA Developers Forum, myself and Mathew Yee, Sr. Application Engineer will present and highlight the features and benefits of Real Intent’s product integration with the comprehensive Verdi debug environment and its application to particular debug challenges such as clock domain crossing (CDC) verification.
Meridian CDC Synopsys VCS Flow
Meridian CDC analyses RTL and gate-level netlists to determine if clock domain crossings between asynchronous domains causes metastability in any signal crossing between the domains. Besides structural and formal methods, Meridian CDC offers the capability to run Synopsys VCS dynamic simulation to confirm that metastability can occur with a specific testbench or test scenario. If a high-coverage testbench is available this is an excellent alternative to formal analysis.
Ascent XV Synopsys VCS Flow
The Ascent X-design and verification system (XV) prevents, detects and isolates issues caused by the propagation of unknowns (‘Xs’) in RTL designs, including Xs that occur during power-on initialization and switching between power modes. Reset and retention optimization minimize block-level standby power and reduce reset routing complexity by assessing and then optimizing the number of flops that require hardware resets and/or retention cells to ensure a complete initialization. The report enables analyzing the initialization state of any power transition.
Ascent can automatically mitigate both X-optimism (which can cover bugs) at the RTL and X-pessimism (unnecessary X-propagation that slows debug) at the gate-level. This mitigation is done by instrumenting the source in conjunction with the Synopsys VCS dynamic simulator.
Ascent and Meridian Debugger Flow with Synopsys Verdi Debug Environment
Real Intent, since 2007, has had an integration with the Synopsys Verdi debug environment which is very popular in the design industry. Our integration features cross-probing from our debugger’s warnings and error reports and their visualization in Verdi. We highlight problem areas by showing only the necessary pruned RTL code in schematic form with custom annotations to aid debug. Additionally we show digital waveforms that illustrate any bug in the users code found by our formal engines. At the VIA Forum event, we will give a 20 minute presentation that gives greater depth and details.
When and Where
Here are the dates and times Synopsys users can visit with Real Intent at SNUG – SV:
SNUG Silicon Valley Designer Community Expo – Monday, Mar. 24, 2014, 4-8 p.m.
VIA Developers Forum – Wednesday, Mar. 26, 2014, 1:45 – 6 p.m.
Santa Clara Convention Center
5001 Great America Pkwy., Santa Clara, CA 95054
See you there!